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KR-20260063509-A - SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

KR20260063509AKR 20260063509 AKR20260063509 AKR 20260063509AKR-20260063509-A

Abstract

A frequency element comprises: a substrate including a first active pattern and a second active pattern spaced apart from each other in a first direction; a first source/drain pattern on the first active pattern; a second source/drain pattern on the second active pattern; a first active contact disposed on the first source/drain pattern; a second active contact disposed on the second source/drain pattern; and a cutting pattern disposed between the first active contact and the second active contact, wherein the cutting pattern comprises: a first cutting pattern extending toward the substrate between the first active contact and the second active contact; and a second cutting pattern disposed on the side and bottom surface of the first cutting pattern and exposing at least a portion of the side surface of the first cutting pattern, and the first direction is a direction parallel to the upper surface of the substrate.

Inventors

  • 백봉관
  • 이준채
  • 백종민
  • 한규희

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20241030

Claims (10)

  1. A substrate comprising a first active pattern and a second active pattern spaced apart from each other in a first direction; A first source/drain pattern on the first active pattern above; A second source/drain pattern on the second active pattern above; A first active contact disposed on the first source/drain pattern above; A second active contact disposed on the second source/drain pattern above; and A cutting pattern disposed between the first active contact and the second active contact, wherein The above cutting pattern is: A first cutting pattern extending toward the substrate between the first active contact and the second active contact; and It includes a second cutting pattern disposed on the side and bottom surface of the first cutting pattern and exposing at least a portion of the side surface of the first cutting pattern, A semiconductor device in which the first direction is a direction parallel to the upper surface of the substrate.
  2. In claim 1, The first cutting pattern and the second cutting pattern are semiconductor devices comprising different materials.
  3. In claim 1, A semiconductor device in which the dielectric constant of the second cutting pattern is lower than the dielectric constant of the first cutting pattern.
  4. In claim 1, The above first cutting pattern includes silicon nitride, and The above second cutting pattern is a semiconductor device comprising silicon carbide.
  5. In claim 1, A first channel pattern on the first active pattern above; A second channel pattern on the second active pattern above; and A gate electrode that crosses the first channel and the second channel pattern, comprising: A semiconductor device in which at least a portion of the second cutting pattern is vertically superimposed with the gate electrode.
  6. In claim 1, A semiconductor device in which the side of the first cutting pattern exposed by the second cutting pattern contacts the first active contact.
  7. In claim 1, A semiconductor device having a thickness of 3 nm to 5 nm of the second cutting pattern.
  8. In claim 1, A semiconductor device in which the lower surface of the second cutting pattern is located at a lower level than the lower surface of the first cutting pattern.
  9. In claim 1, The above first cutting pattern includes a first side and a second side facing in a second direction, and The second cutting pattern includes first cutting portions spaced apart from each other in the second direction, and Each of the first cutting portions covers the first side of the first cutting pattern and the second side of the first cutting pattern, and A semiconductor device in which the second direction is parallel to the upper surface of the substrate and intersects the first direction.
  10. In claim 9, A semiconductor device in which the first distance of the first cutting portions in the second direction is greater than the width of the first active contact in the second direction.

Description

Semiconductor Device and Method for Manufacturing the Same The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a field-effect transistor and a method for manufacturing the same. Semiconductor devices include integrated circuits composed of MOS (Metal Oxide Semiconductor) FETs. As the size and design rules of semiconductor devices gradually shrink, the scale-down of MOS FETs is also accelerating. The operating characteristics of semiconductor devices may degrade as the size of MOS FETs is reduced. Accordingly, various methods are being studied to form semiconductor devices with superior performance while overcoming the limitations associated with high integration of semiconductor devices. FIGS. 1 to 3 are conceptual diagrams for explaining logic cells of a semiconductor device according to embodiments of the present invention. FIG. 4 is a plan view of a semiconductor device according to embodiments of the present invention. FIGS. 5a to 5e are cross-sectional views of semiconductor devices according to embodiments of the present invention. Fig. 5f is an enlarged view of M in Fig. 4. Fig. 5g is an enlarged view of N in Fig. 5c. Fig. 5H is an enlarged view of O in Fig. 5D. FIGS. 6a to 17H are drawings illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention. FIG. 18 is a plan view of a semiconductor device according to some embodiments of the present invention. FIGS. 19a to 19e are cross-sectional views of semiconductor devices according to some embodiments of the present invention. FIG. 19f is an enlarged view of M in FIG. 18. FIG. 19g is an enlarged view of N in FIG. 19c. FIG. 19H is an enlarged view of O in FIG. 19D. FIGS. 20 to 21H are drawings illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. The present invention will be described in detail below by explaining embodiments of the present invention with reference to the attached drawings. FIGS. 1 to 3 are conceptual diagrams for explaining logic cells of a semiconductor device according to embodiments of the present invention. Referring to FIG. 1, a Single Height Cell (SHC) may be provided. Specifically, a first power line (M1_R1) and a second power line (M1_R2) may be provided on a substrate (100). The first power line (M1_R1) may be a channel for providing a drain voltage (VDD), for example, a power voltage. The second power line (M1_R2) may be a channel for providing a source voltage (VSS), for example, a ground voltage. A single height cell (SHC) may be defined between the first power line (M1_R1) and the second power line (M1_R2). The single height cell (SHC) may include one PMOSFET region (PR) and one NMOSFET region (NR). In other words, the single height cell (SHC) may have a CMOS structure provided between the first power line (M1_R1) and the second power line (M1_R2). Each of the PMOSFET region (PR) and the NMOSFET region (NR) may have a first width (W1) in a first direction (D1). The length of the single height cell (SHC) in the first direction (D1) may be defined as a first height (HE1). The first height (HE1) may be substantially equal to the distance (e.g., pitch) between the first power line (M1_R1) and the second power line (M1_R2). A single height cell (SHC) can constitute a single logic cell. In this specification, a logic cell may refer to a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). That is, a logic cell may include transistors for constituting a logic element and wirings connecting said transistors to each other. Referring to FIG. 2, a double height cell (DHC) may be provided. Specifically, a first power line (M1_R1), a second power line (M1_R2), and a third power line (M1_R3) may be provided on a substrate (100). The first power line (M1_R1) may be positioned between the second power line (M1_R2) and the third power line (M1_R3). The third power line (M1_R3) may be a passage through which a drain voltage (VDD) is provided. A double height cell (DHC) may be defined between the second power wiring (M1_R2) and the third power wiring (M1_R3). The double height cell (DHC) may include a first PMOSFET region (PR1), a second PMOSFET region (PR2), a first NMOSFET region (NR1), and a second NMOSFET region (NR2). The first NMOSFET region (NR1) may be adjacent to the second power line (M1_R2). The second NMOSFET region (NR2) may be adjacent to the third power line (M1_R3). The first and second PMOSFET regions (PR1, PR2) may be adjacent to the first power line (M1_R1). In a planar view, the first power line (M1_R1) may be positioned between the first and second PMOSFET regions (PR1, PR2). The length of the double height cell (DHC) in the first direction (D1) can be defined as the second height (HE2). The second height (HE2) may be approximately twice the first height (HE1) of