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KR-20260063589-A - Semiconductor device

KR20260063589AKR 20260063589 AKR20260063589 AKR 20260063589AKR-20260063589-A

Abstract

A semiconductor device capable of improving device performance and reliability is provided. The semiconductor device comprises a substrate including an NMOS region and a PMOS region, a first transistor disposed in the NMOS region including a first gate stack and a first source/drain region disposed on at least one side of the first gate stack, and a second transistor disposed in the PMOS region including a second gate stack and a second source/drain region disposed on at least one side of the second gate stack, wherein the first gate stack includes a first high dielectric constant insulating film, an insertion layer, a first metal layer, and a first protective layer sequentially stacked in a first direction, and the second gate stack includes a second high dielectric constant insulating film, a second metal layer, and a second protective layer sequentially stacked in a first direction, wherein the concentration of oxygen included in the first protective layer is higher than the concentration of oxygen included in the first metal layer, and the concentration of oxygen included in the second protective layer is higher than the concentration of oxygen included in the second metal layer.

Inventors

  • 안덕래
  • 송희찬
  • 이동수
  • 김택중
  • 박상훈

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20241030

Claims (10)

  1. A substrate including an NMOS region and a PMOS region; A first transistor disposed in the NMOS region, comprising a first gate stack and a first source/drain region disposed on at least one side of the first gate stack; and A second transistor disposed in the above PMOS region, comprising a second transistor including a second gate stack and a second source/drain region disposed on at least one side of the second gate stack, and The first gate stack comprises a first high dielectric constant insulating film, an insertion layer, a first metal layer, and a first protective layer sequentially stacked in a first direction, and The second gate stack comprises a second high dielectric constant insulating film, a second metal layer, and a second protective layer sequentially stacked in the first direction, and The oxygen concentration contained in the first protective layer is higher than the oxygen concentration contained in the first metal layer, and A semiconductor device in which the oxygen concentration contained in the second protective layer is higher than the oxygen concentration contained in the second metal layer.
  2. In Article 1, The thickness of the first protective layer in the first direction is smaller than the thickness of the first metal layer in the first direction, and A semiconductor device in which the thickness of the second protective layer in the first direction is smaller than the thickness of the second metal layer in the first direction.
  3. In Article 1, The thickness of the first protective layer in the first direction is the same as the thickness of the second protective layer in the first direction, and A semiconductor device in which the thickness of the first metal layer in the first direction is the same as the thickness of the second metal layer in the first direction.
  4. In Article 1, A semiconductor device in which the thickness of the first high dielectric constant insulating film in the first direction is smaller than the thickness of the second high dielectric constant insulating film in the first direction.
  5. In Article 1, The first protective layer comprises an oxide or oxynitride of an element included in the first metal layer, and A semiconductor device in which the second protective layer comprises an oxide or oxynitride of an element included in the second metal layer.
  6. In Article 1, A semiconductor device in which the concentration of lanthanum (La) contained in the second high dielectric constant insulating film is higher than the concentration of lanthanum contained in the first high dielectric constant insulating film.
  7. A substrate comprising a cell array region including a buried gate structure and a peripheral region including an NMOS region and a PMOS region having different conductivity types; A first transistor disposed in the NMOS region, comprising a first gate stack and a first source/drain region disposed on at least one side of the first gate stack; and A second transistor disposed in the above PMOS region, comprising a second transistor including a second gate stack and a second source/drain region disposed on at least one side of the second gate stack, and The first gate stack comprises a first high dielectric constant insulating film, an insertion layer, a first metal layer, and a first protective layer sequentially stacked in a first direction, and The second gate stack comprises a second high dielectric constant insulating film, a second metal layer, and a second protective layer sequentially stacked in the first direction, and The oxygen concentration contained in the first protective layer is higher than the oxygen concentration contained in the first metal layer, and A semiconductor device in which the oxygen concentration contained in the second protective layer is higher than the oxygen concentration contained in the second metal layer.
  8. In Article 7, A semiconductor device in which the concentration of lanthanum (La) contained in the second high dielectric constant insulating film is higher than the concentration of lanthanum contained in the first high dielectric constant insulating film.
  9. In Article 7, The first protective layer comprises an oxide or oxynitride of an element included in the first metal layer, and A semiconductor device in which the second protective layer comprises an oxide or oxynitride of an element included in the second metal layer.
  10. A substrate including an NMOS region and a PMOS region; A first transistor disposed in the NMOS region, comprising a first gate stack and a first source/drain region disposed on at least one side of the first gate stack; and A second transistor disposed in the above PMOS region, comprising a second transistor including a second gate stack and a second source/drain region disposed on at least one side of the second gate stack, and The first gate stack comprises a first high dielectric constant insulating film, a first metal layer, and a first protective layer sequentially stacked in a first direction, and The second gate stack comprises a second high dielectric constant insulating film, a second metal layer, and a second protective layer sequentially stacked in the first direction, and The oxygen concentration contained in the first protective layer is higher than the oxygen concentration contained in the first metal layer, and The oxygen concentration contained in the second protective layer is higher than the oxygen concentration contained in the second metal layer, and A semiconductor device in which the concentration of lanthanum (La) contained in the first high dielectric constant insulating film is higher than the concentration of lanthanum contained in the second high dielectric constant insulating film.

Description

Semiconductor device The present invention relates to a semiconductor device. Semiconductor memory devices such as DRAM (dynamic random access memory) may include a cell array region and a peripheral region or a core-peri region. In particular, the peripheral region or the core-peri region may include a region where PMOS transistors are formed and a region where NMOS transistors are formed. Recently, gate structures having different structures are placed in each of the region where PMOS transistors are formed and the region where NMOS transistors are formed. FIG. 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. FIG. 2 is a cross-sectional view illustrating a semiconductor device according to other embodiments of the present invention. FIG. 3 is a plan view of a substrate for illustrating a semiconductor device according to some embodiments of the present invention. Figure 4 is a schematic layout diagram showing an enlarged view of the first area (R1) of Figure 3. Figure 5 is a cross-sectional view taken along A-A', BB', and C-C' of Figure 4. FIGS. 6 to 14 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments of the present invention. In this specification, although terms such as "first," "second," etc. are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention. FIG. 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. Referring to FIG. 1, a semiconductor device according to some embodiments of the present invention may include a substrate (100), a first gate stack (G1), a first gate spacer (181), a second gate stack (G2), and a second gate spacer (182). The substrate (100) may include an NMOS region (RN) and a PMOS region (RP). The NMOS region (RN) and the PMOS region (RP) may be separate regions or connected regions. Transistors of different conductivity types may be placed in each of the NMOS region (RN) and the PMOS region (RP). For example, an NMOS transistor may be formed in the NMOS region (RN). Additionally, a PMOS transistor may be formed in the PMOS region (RP). The substrate (100) may be, for example, bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may be a silicon substrate or may include other materials, for example, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Or, the substrate (100) may be a base substrate on which an epitaxial layer is formed. The substrate (100) may include device isolation films (110). A plurality of device isolation films (110) may be disposed within the substrate (100). For example, the device isolation films (110) may be formed within the substrate (100) to define an NMOS region (RN) and a PMOS region (RP), respectively. Additionally, at least one transistor may be disposed between adjacent device isolation films (110). The device isolation layer (110) may include silicon oxide, silicon nitride, or a combination thereof, but the technical concept of the present invention is not limited thereto. The device isolation layer (110) may be a single layer made of one type of insulating material, or a multilayer made of a combination of several types of insulating materials. A first transistor may be disposed in an NMOS region (RN). The first transistor may include a first gate stack (G1), a first gate spacer (181), and a first source/drain region (105). The first transistor may be an n-type planar transistor. The first gate spacer (181) may be placed on at least one side of the first gate stack (G1). For example, the first gate spacer (181) may be placed on both sides of the first gate stack (G1). The first gate spacer (181) may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide ( SiO2 ), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), or a combination thereof. The first gate stack (G1) may include a first interface insulating film (121), a first high dielectric constant insulating film (131), an insertion layer (210), a first metal layer (141), a first protective layer (151), a first conductive film structure (161), and a first hard mask pattern (171) that are sequentially laminated. The first interface insulating film (121) may be disposed directly on the substrate. The first interface insulating film (121) may include, for example, a silicon oxide film or a silicon oxynitride film. The first high dielectric constant insulating film (131) may be disposed on the first interface insula