KR-20260063616-A - SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package according to the technical concept of the present invention comprises a package substrate, a pair of first semiconductor chips mounted on the package substrate and facing each other in a horizontal direction, a pair of second semiconductor chips mounted on the pair of first semiconductor chips and facing each other in a horizontal direction, a pair of molding members covering the periphery of the pair of second semiconductor chips on the pair of first semiconductor chips, and an encapsulation covering the periphery of the pair of first semiconductor chips and a part of the pair of molding members on the package substrate, wherein the width of each of the pair of molding members along the horizontal direction is greater in the second width in the second region where the pair of second semiconductor chips do not face each other than in the first region where the pair of second semiconductor chips face each other, and a groove of a predetermined depth is formed in each of the pair of second semiconductor chips in the direction where the pair of second semiconductor chips face each other.

Inventors

• 이동국
• 백승덕

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241030

Claims (20)

1. Package substrate; A pair of first semiconductor chips mounted on the above package substrate and facing each other in a horizontal direction; A pair of second semiconductor chips mounted on the pair of first semiconductor chips and facing each other in the horizontal direction; A pair of molding members covering the periphery of the pair of second semiconductor chips on the pair of first semiconductor chips; and On the above package substrate, the encapsulation covering the periphery of the pair of first semiconductor chips and a portion of the pair of molding members; The width of each of the above-mentioned pair of molding members along the horizontal direction is such that the second width in the second region where the pair of second semiconductor chips do not face each other is greater than the first width in the first region where the pair of second semiconductor chips face each other, and A groove of a predetermined depth is formed in each of the pair of second semiconductor chips in a direction in which the pair of second semiconductor chips face each other. Semiconductor package.
2. In paragraph 1, A semiconductor package characterized in that the grooves of the pair of second semiconductor chips have a mirror-image symmetric structure with respect to the first region.
3. In paragraph 2, A semiconductor package characterized in that the above pair of molding members fill all the grooves of the above pair of second semiconductor chips.
4. In paragraph 1, The groove is formed by cutting a portion of the uppermost surface of each of the pair of second semiconductor chips and a portion of a side wall adjacent to the first region, and A semiconductor package characterized in that the side wall and the bottom surface of the above groove meet each other at a rounded corner.
5. In paragraph 1, The groove is formed by cutting a portion of the uppermost surface of each of the pair of second semiconductor chips and a portion of a side wall adjacent to the first region, and A semiconductor package characterized in that the above groove has a stepped shape.
6. In paragraph 1, A pair of physical signal connection structures for transmitting and receiving signals between the pair of second semiconductor chips are disposed adjacent to the first region, and A semiconductor package characterized in that the grooves of the pair of second semiconductor chips overlap in a vertical direction with the pair of physical signal connection structures.
7. In paragraph 6, A semiconductor package characterized in that the above pair of physical signal connection structures are electrically connected to each other through the above pair of first semiconductor chips and the package substrate.
8. In paragraph 1, The sidewalls of each of the pair of first semiconductor chips and the sidewalls of each of the pair of molding members are coplanar with each other in the vertical direction, and The vertical length of one sidewall adjacent to the first region of each of the pair of second semiconductor chips is smaller than the vertical length of the other sidewall adjacent to the second region, and A semiconductor package characterized in that the above encapsulation has a rounded upper surface in the first region and a slanted sidewall in the second region.
9. In paragraph 8, The vertical level of the uppermost surface of the above pair of molding members is substantially the same as the vertical level of the uppermost surface of the above pair of second semiconductor chips, and The vertical level of the lower surface of the grooves of the pair of second semiconductor chips is lower than the vertical level of the upper surface of the pair of second semiconductor chips, and A semiconductor package characterized in that the vertical level of the uppermost surface of the above pair of molding members is higher than the vertical level of the uppermost surface of the above encapsulation.
10. In paragraph 1, A semiconductor package characterized in that the width along the horizontal direction of each of the pair of second semiconductor chips is smaller than the width along the horizontal direction of each of the pair of first semiconductor chips.
11. Package substrate; A pair of first semiconductor chips mounted on the above package substrate and facing each other in a horizontal direction; A pair of second semiconductor chips mounted on the pair of first semiconductor chips and facing each other in the horizontal direction; A pair of molding members covering the periphery of the pair of second semiconductor chips on the pair of first semiconductor chips; and On the above package substrate, the encapsulation covering the periphery of the pair of first semiconductor chips and a portion of the pair of molding members; The width of each of the above-mentioned pair of molding members along the horizontal direction is such that the second width in the second region where the pair of second semiconductor chips do not face each other is greater than the first width in the first region where the pair of second semiconductor chips face each other, and Adjacent to the first region, a first groove of a first depth is formed in each of the pair of second semiconductor chips, and Adjacent to the second region, a second groove having a second depth smaller than the first depth is formed in each of the pair of second semiconductor chips. Semiconductor package.
12. In Paragraph 11, A semiconductor package characterized in that the first width along the horizontal direction of the first groove is larger than the second width along the horizontal direction of the second groove.
13. In Paragraph 12, The first grooves of the pair of second semiconductor chips have a mirror-image symmetric structure with respect to the first region, A semiconductor package characterized in that the second grooves of the pair of second semiconductor chips have a mirror-image symmetric structure with respect to the first region.
14. In Paragraph 11, A semiconductor package characterized in that the above pair of molding members fill both the first grooves and the second grooves of the above pair of second semiconductor chips.
15. In Paragraph 11, A pair of physical signal connection structures for transmitting and receiving signals between the pair of second semiconductor chips are disposed adjacent to the first region, and A semiconductor package characterized in that the first grooves of the pair of second semiconductor chips overlap in a vertical direction with the pair of physical signal connection structures, and the second grooves do not overlap in a vertical direction with the pair of physical signal connection structures.
16. Package substrate; A pair of first semiconductor chips mounted on the above package substrate and facing each other in a horizontal direction; A second semiconductor chip mounted on one of the above pair of first semiconductor chips; A third semiconductor stack mounted on the remainder of the above pair of first semiconductor chips; A pair of molding members covering the periphery of the second semiconductor chip and the periphery of the third semiconductor stack on the above pair of first semiconductor chips; and On the above package substrate, the encapsulation covering the periphery of the pair of first semiconductor chips and a portion of the pair of molding members; The width of the molding member disposed around the second semiconductor chip along the horizontal direction is such that the second width in the second region where the second semiconductor chip and the third semiconductor stack do not face each other is greater than the first width in the first region where the second semiconductor chip and the third semiconductor stack face each other. A groove of a predetermined depth is formed in the second semiconductor chip in a direction in which the second semiconductor chip and the third semiconductor stack face each other. Semiconductor package.
17. In Paragraph 16, The above groove is formed by cutting a part of the uppermost surface of the second semiconductor chip and a part of a side wall adjacent to the first region, and A semiconductor package characterized in that the side wall and the bottom surface of the above groove meet each other at a rounded corner.
18. In Paragraph 16, The above third semiconductor stack includes a stacked structure of a plurality of semiconductor dies, and A semiconductor package characterized in that the plurality of semiconductor dies are electrically connected to each other through a plurality of silicon through-vias.
19. In Paragraph 18, A semiconductor package characterized by having a top layer groove of a predetermined depth formed in the top layer semiconductor die of the plurality of semiconductor dies.
20. In Paragraph 19, A semiconductor package characterized in that the groove of the second semiconductor chip and the top layer groove of the third semiconductor stack face each other.

Description

Semiconductor Package The technical field of the present invention relates to semiconductor packages, and more specifically, to a semiconductor package for efficiently mounting semiconductor chips within a limited semiconductor package structure. Recently, the demand for portable devices in the electronics market has been rapidly increasing, leading to a continuous demand for the miniaturization and lightweighting of electronic components mounted on these products. To achieve this miniaturization and lightweighting of electronic components, not only is technology required to reduce the individual size of mounted components, but also semiconductor packaging technology to integrate multiple individual components into a single package. In particular, as high-performance and high-capacity semiconductors are required, the number of semiconductor chips mounted on a semiconductor package increases. However, due to spatial constraints within the semiconductor package, technology is required to overcome these spatial limitations by changing the arrangement method of the semiconductor chips. FIG. 1 is a cross-sectional view showing the main components of a semiconductor package according to one embodiment of the technical concept of the present invention. FIGS. 2 to 6 are cross-sectional views showing the main components of a semiconductor package according to another embodiment of the technical concept of the present invention. FIGS. 7 to 14 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the technical concept of the present invention in the order of process. FIGS. 15 to 19 are plan views showing the main configurations of a semiconductor package according to another embodiment of the technical concept of the present invention. FIG. 20 is a schematic diagram showing the configuration of a semiconductor package according to embodiments of the technical concept of the present invention. Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. FIG. 1 is a cross-sectional view showing the main components of a semiconductor package according to one embodiment of the technical concept of the present invention. Referring to FIG. 1, a semiconductor package (1) comprises a package substrate (100), a pair of first semiconductor chips (110R, 110L), a pair of second semiconductor chips (120R, 120L), an underfill (UF), a molding member (MB), and an encapsulation (EC). In a System in Package that integrates multiple individual semiconductor chips into a single package, the number of semiconductor chips constituting the semiconductor package (1) may vary depending on the use of the semiconductor package (1). That is, although the drawing shows a total of four semiconductor chips mounted on the package substrate (100), the number of semiconductor chips constituting the semiconductor package (1) is not limited to the number shown in the drawing. Here, for the sake of convenience of explanation, semiconductor chips of the same type are grouped together for explanation. That is, the first semiconductor chip and the second semiconductor chip are used to mean that there are two types of semiconductor chips of different kinds. The package substrate (100) may include a body portion (101), a lower protective layer (not shown), and an upper protective layer (not shown) as a support substrate. The package substrate (100) may be formed based on a printed circuit board (PCB), a wafer substrate, a ceramic substrate, a glass substrate, etc. In an embodiment according to the technical concept of the present invention, the package substrate (100) may be a printed circuit board. In the above printed circuit board, the body portion (101) can typically be formed into a thin film by compressing a polymer material such as a thermosetting resin, an epoxy resin such as FR-4 (Flame Retardant 4), BT (Bismaleimide Triazine), ABF (Ajinomoto Build-up Film), or a phenolic resin to a certain thickness, and then applying copper foil to both sides and forming wiring, which is a transmission path for electrical signals, through patterning. The above package substrate (100) may include a lower electrode pad (not shown) and an upper electrode pad (103). Additionally, a wiring layer (105) is formed on the package substrate (100), and the wiring layer (105) may be electrically connected to first and second semiconductor chips (110R, 110L, 120R, 120L) connected to the upper electrode pad (103) on the upper surface of the package substrate (100). An external connection terminal (107) may be disposed on the lower electrode pad on the lower surface of the package substrate (100). The package substrate (100) may be electrically connected to and mounted on a module substrate (not shown) or a system board (not shown) of an electronic product through the external connection terminal (107). A pair of first semiconductor