KR-20260063619-A - Stacked integrated circuit devices

Abstract

A stacked integrated circuit device according to the present invention comprises: a plurality of nanosheet stacking structures arranged in rows and columns along a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each comprising a lower nanosheet stacking structure and an upper nanosheet stacking structure on the lower nanosheet stacking structure; a gate separation portion interposed between the lower nanosheet stacking structure and the upper nanosheet stacking structure of each of the plurality of nanosheet stacking structures; a lower gate electrode surrounding the lower nanosheet stacking structure of each of the plurality of nanosheet stacking structures; an upper gate electrode surrounding the upper nanosheet stacking structure of each of the plurality of nanosheet stacking structures; a lower gate cut structure disposed between two lower nanosheet stacking structures included in the two nanosheet stacking structures in at least one of the spaces between two nanosheet stacking structures adjacent along the second horizontal direction among the plurality of nanosheet stacking structures; and an upper gate cut structure disposed on the lower gate cut structure between two upper nanosheet stacking structures included in the two nanosheet stacking structures. and a bonding gate cut structure disposed between the two nanosheet stacking structures in at least one other space among the spaces between the two nanosheet stacking structures adjacent along the second horizontal direction among the plurality of nanosheet stacking structures; wherein the upper gate electrode extends along the side of the bonding gate cut structure and is connected to the lower gate electrode.

Inventors

• 문병호
• 황동훈
• 김민우

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241030

Claims (10)

1. A plurality of nanosheet stacking structures arranged in rows and columns along a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each comprising a lower nanosheet stacking structure and an upper nanosheet stacking structure on the lower nanosheet stacking structure; A gate separation portion interposed between the lower nanosheet stacking structure and the upper nanosheet stacking structure of each of the plurality of nanosheet stacking structures; A lower gate electrode surrounding each of the plurality of nanosheet stacked structures; An upper gate electrode surrounding each of the upper nanosheet stacking structures of the plurality of nanosheet stacking structures; Among the plurality of nanosheet stacked structures, in at least one of the spaces between two nanosheet stacked structures adjacent along the second horizontal direction, a lower gate cut structure disposed between two lower nanosheet stacked structures comprising the two nanosheet stacked structures, and an upper gate cut structure disposed on the lower gate cut structure between two upper nanosheet stacked structures comprising the two nanosheet stacked structures; and Among the plurality of nanosheet stacked structures, a bonding gate cut structure disposed between the two nanosheet stacked structures in at least one other space among the spaces between two adjacent nanosheet stacked structures along the second horizontal direction; The upper gate electrode is a stacked integrated circuit device that extends along the side of the combined gate cut structure and is connected to the lower gate electrode.
2. In Article 1, A stacked integrated circuit device characterized in that, in the second horizontal direction, the portion of the lower gate electrode surrounding the lower nanosheet stacked structure and the upper gate electrode surrounding the upper nanosheet stacked structure, which are located on at least one side of the lower gate cut structure and the upper gate cut structure on the lower gate cut structure, are spaced apart from each other and are not connected.
3. In Article 1, The width of the upper surface of the lower gate cut structure is greater than the width of the lower surface of the upper gate cut structure disposed on the lower gate cut structure, and A stacked integrated circuit device characterized in that the upper gate electrode has a protrusion that protrudes in a vertical direction from a portion overlapping with the gate separation portion to a portion overlapping with the lower gate cut structure.
4. In Paragraph 3, A stacked integrated circuit device characterized in that a portion of the upper surface of the lower gate cut structure is covered by the lower surface of the upper gate cut structure, and another portion of the upper surface of the lower gate cut structure is covered by the lower surface of the protrusion.
5. In Article 1, The lower nanosheet stacking structure comprises a plurality of lower nanosheets spaced apart from each other along the vertical direction, and the upper nanosheet stacking structure comprises a plurality of upper nanosheets spaced apart from each other along the vertical direction. A stacked integrated circuit device characterized in that, in the second horizontal direction, the horizontal width of each of the plurality of lower nanosheets is greater than the horizontal width of each of the plurality of upper nanosheets.
6. A plurality of nanosheet stacking structures arranged in rows and columns along a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each comprising a lower nanosheet stacking structure and an upper nanosheet stacking structure on the lower nanosheet stacking structure; An intermediate insulating layer interposed between the lower nanosheet stacking structure and the upper nanosheet stacking structure of each of the plurality of nanosheet stacking structures; A lower gate electrode surrounding each of the plurality of nanosheet stacked structures; An upper gate electrode surrounding each of the upper nanosheet stacking structures of the plurality of nanosheet stacking structures; Among the plurality of nanosheet stacked structures, in at least one of the spaces between two nanosheet stacked structures adjacent along the second horizontal direction, a lower gate cut structure disposed between two lower nanosheet stacked structures comprising the two nanosheet stacked structures, and an upper gate cut structure disposed on the lower gate cut structure between two upper nanosheet stacked structures comprising the two nanosheet stacked structures; and Among the plurality of nanosheet stacked structures, a bonding gate cut structure disposed between the two nanosheet stacked structures in at least one other space among the spaces between two adjacent nanosheet stacked structures along the second horizontal direction; A stacked integrated circuit device comprising: an upper gate electrode, a connecting extension extending along the side of the combined gate cut structure and connected to the lower gate electrode, and a protrusion protruding in a vertical direction from a portion overlapping with the intermediate insulating layer to a portion overlapping with the lower gate cut structure.
7. In Article 6, The width of the upper surface of the lower gate cut structure is greater than the width of the lower surface of the upper gate cut structure disposed on the lower gate cut structure, and A stacked integrated circuit device characterized in that a portion of the upper surface of the lower gate cut structure is covered by the lower surface of the upper gate cut structure, and another portion of the upper surface of the lower gate cut structure is covered by the lower surface of the protrusion.
8. In Article 6, A stacked integrated circuit device characterized in that, in the second horizontal direction, the portion of the lower gate electrode surrounding the lower nanosheet stacked structure and the upper gate electrode surrounding the upper nanosheet stacked structure, which includes the nanosheet stacked structure located on at least one side of the lower gate cut structure and the upper gate cut structure, are spaced apart from each other and are not connected, with the intermediate insulating layer and the lower gate cut structure in between.
9. In Article 6, The upper nanosheet stacking structure comprises a plurality of upper nanosheets that are spaced apart from each other along the vertical direction and each have a first horizontal width in the second horizontal direction. A stacked integrated circuit device characterized in that the above-described lower nanosheet stacking structure is spaced apart from each other along the vertical direction and includes a plurality of lower nanosheets each having a second horizontal width greater than the first horizontal width in the second horizontal direction.
10. A plurality of nanosheet stacking structures comprising: a lower nanosheet stacking structure composed of a plurality of lower nanosheets arranged in rows and columns along a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each spaced apart from each other along a vertical direction; and an upper nanosheet stacking structure composed of a plurality of upper nanosheets spaced apart from each other along the vertical direction on the lower nanosheet stacking structure; A gate separation portion interposed between the lower nanosheet stacking structure and the upper nanosheet stacking structure of each of the plurality of nanosheet stacking structures; A lower gate electrode surrounding each of the plurality of nanosheet stacked structures; An upper gate electrode surrounding each of the upper nanosheet stacking structures of the plurality of nanosheet stacking structures; Among the plurality of nanosheet stacked structures, in at least one of the spaces between two nanosheet stacked structures adjacent along the second horizontal direction, a lower gate cut structure disposed between two lower nanosheet stacked structures comprising the two nanosheet stacked structures, and an upper gate cut structure disposed on the lower gate cut structure between two upper nanosheet stacked structures comprising the two nanosheet stacked structures; and Among the plurality of nanosheet stacked structures, a bonding gate cut structure disposed between the two nanosheet stacked structures in at least one other space among the spaces between two adjacent nanosheet stacked structures along the second horizontal direction; The upper gate electrode comprises a connecting extension that extends along the side of the combined gate cut structure and is connected to the lower gate electrode, and a protrusion that protrudes from a portion overlapping the gate separation portion in the vertical direction to a portion overlapping the lower gate cut structure and covers a portion of the upper surface of the lower gate cut structure. A stacked integrated circuit device in which, in the second horizontal direction, the horizontal width of each of the plurality of lower nanosheets is greater than the horizontal width of each of the plurality of upper nanosheets.

Description

Stacked integrated circuit devices The present invention relates to an integrated circuit device, and in particular to a stacked integrated circuit device. With the advancement of electronic technology, the down-scaling of integrated circuit devices is progressing rapidly. In addition, stacked integrated circuit devices are being researched to further increase the integration density of integrated circuit devices. FIG. 1 is an equivalent circuit diagram of a stacked integrated circuit element according to exemplary embodiments of the present invention. FIG. 2 is a schematic layout for explaining a method for manufacturing a stacked integrated circuit device according to exemplary embodiments of the present invention, and FIGS. 3a to 3c, FIGS. 4a to 4c, FIGS. 5a to 5c, FIGS. 6a to 6c, FIGS. 7a to 7c, FIGS. 8a to 8c, FIGS. 9a to 9c, FIGS. 10a to 10c, FIGS. 11a to 11c, FIGS. 12a to 12c, FIGS. 13a to 13c, FIGS. 14a to 14c, and FIGS. 15a to 15c are cross-sectional views for explaining a method for manufacturing a stacked integrated circuit device according to exemplary embodiments of the present invention. FIGS. 16a to 16c are cross-sectional views showing stacked integrated circuit elements according to exemplary embodiments of the present invention. FIG. 17 is a cross-sectional view showing a stacked integrated circuit element according to exemplary embodiments of the present invention. FIG. 1 is an equivalent circuit diagram of a stacked integrated circuit element according to exemplary embodiments of the present invention. Referring to FIG. 1, a stacked integrated circuit element (1000) may include a plurality of transistors. The stacked integrated circuit element (1000) may include at least one pair of cross-coupled transistors. "Cross-coupled" means that two similar devices are connected in parallel, but the output of each device is transferred to the input of the other device. For example, cross-coupled NAND gates (Negative-AND gates) can form an SR flip-flop or a latch. In some embodiments, at least some of the plurality of transistors included in the stacked integrated circuit element (1000) may form a static random access memory (SRAM), but are not limited thereto. SRAM is a type of random access memory that uses a latching circuit to store one or more bits. FIG. 1 illustrates an equivalent circuit diagram of an SRAM included in the stacked integrated circuit element (1000). The SRAM includes six metal oxide semiconductor field-effect transistors (MOSFETs). The six MOSFETs may consist of two pull-up transistors (PU), two pull-down transistors (PD), and two pass-gate transistors (PG). The corresponding pull-up transistors (PU) and pull-down transistors (PD) may form an inverter, and the two inverters formed by the two pull-up transistors (PU) and two pull-down transistors (PD) may be cross-connected. For example, the gate of the pull-up transistor (PU) and the gate of the pull-down transistor (PD) of one inverter may be connected to the source of the pull-up transistor (PU) and the source of the pull-down transistor (PD) of the other inverter. The two pass-gate transistors (PG) serve to control access during read and write operations for the memory cell formed by the two cross-connected inverters. For example, the source of one pass gate transistor (PG) can be electrically connected to the source of one inverter’s pull-up transistor (PU) and the source of one pull-down transistor (PD), and the gate of another inverter’s pull-up transistor (PU) and the gate of one pull-down transistor (PD), the gate of one pass gate transistor (PG) can be electrically connected to the word line (WL), and the drain of one pass gate transistor (PG) can be electrically connected to the bit line (BL). The source of another pass gate transistor (PG) can be electrically connected to the gate of one inverter’s pull-up transistor (PU) and the gate of one pull-down transistor (PD), and the source of another inverter’s pull-up transistor (PU) and the source of one pull-down transistor (PD), the gate of one pass gate transistor (PG) can be electrically connected to the word line (WL), and the drain of another pass gate transistor (PG) can be connected to the complementary bit line (BLB). The drain of the pull-up transistor (PU) can be connected to the power supply (VDD), and the drain of the pull-down transistor (PD) can be connected to the ground (VSS). During a read operation, the word line (WL) can be set to high (e.g., logic state "1") to enable access to the memory cell by two pass gate transistors (PG). By enabling the word line (WL), the value of the memory cell (e.g., "0" or "1") can be read through the bit line (BL) and/or the complementary bit line (BLB). For example, if the logic state "1" is stored in the memory cell and the word line (WL) turns on the two pass gate transistors (PG), the bit line (BL) can read "1" and the complementary bit line (BLB) can read "0". During a write operation, for example, when a command to