KR-20260063692-A - GATE DRIVER AND DISPLAY DEVICE INCLUDING THE SAME

KR20260063692AKR 20260063692 AKR20260063692 AKR 20260063692AKR-20260063692-A

Abstract

A gate driving unit according to an embodiment and a display device including the same are disclosed. The gate driving unit includes a plurality of signal transmission units that are dependently connected via a carry line to which a carry signal is applied from a previous signal transmission unit and output a gate signal according to a clock signal, and the nth (n is a positive integer) signal transmission unit includes a first output circuit that outputs a carry signal based on a carry signal from a previous signal transmission unit and the clock signal, a selection circuit that receives a carry signal output from the first output circuit and selectively outputs the received carry signal according to a voltage level of a selected data voltage, and an output circuit that outputs a gate signal based on a carry signal output from the selection circuit and the clock signal.

Inventors

이부흥

Assignees

엘지디스플레이 주식회사

Dates

Publication Date: 20260507
Application Date: 20241031

Claims (19)

It includes a plurality of signal transmission units that are dependently connected via a carry line to which a carry signal is applied from a previous signal transmission unit and output a gate signal according to a clock signal, The nth (n is a positive integer) signal transmission unit, A first output circuit that outputs a carry signal based on a carry signal from a previous signal transmission unit and the clock signal; A selection circuit that receives a carry signal output from the first output circuit and selectively transmits the received carry signal according to the voltage level of the selected data voltage; and A gate driving unit comprising a second output circuit that outputs a gate signal based on a carry signal transmitted from the selection circuit and the clock signal.
In paragraph 1, The above selection circuit is, When the voltage level of the above-mentioned selected data voltage is the gate-on voltage level, the above-mentioned carry signal is output, and A gate driver that does not transmit the above carry signal when the gate off voltage level is at the gate off voltage level.
In paragraph 1, The above selection circuit is, A first transistor comprising a gate electrode to which a selection signal is applied, a first electrode to which the selection data voltage is applied, and a second electrode connected to a first node, A second transistor comprising a gate electrode connected to the first node, a first electrode to which the carry signal is applied, and a second electrode connected to an output node; and A gate driver comprising a gate electrode connected to the first node, a first electrode connected to the output node, and a third transistor having a second electrode to which a low potential voltage is applied.
In paragraph 3, The gate driver, wherein the second and third transistors are different transistors among a P-channel transistor and an n-channel transistor.
In paragraph 3, A gate driver further comprising a capacitor connected between the first node and ground.
In paragraph 5, The above selection circuit is, When the transistor is turned on by the above selection signal, the selection data voltage is stored in the capacitor, and A gate driver, wherein when the second transistor is turned on by the selected data voltage stored in the capacitor, the carry signal is output through the output node.
In paragraph 6, The above selection circuit is, A gate driver, wherein when the third transistor is turned on by the selected data voltage stored in the capacitor, the low potential voltage is output through the output node.
In paragraph 1, Each of the first and second output circuits above includes a pull-up transistor and a pull-down transistor, and The pull-up transistor includes a gate electrode connected to a first control node, a first electrode connected to a low potential voltage, and a second electrode connected to an output node. The above pull-down transistor comprises a gate driving unit including a gate electrode connected to a second control node, a first electrode connected to an output node, and a second electrode connected to a high potential voltage.
In paragraph 1, Each of the first and second output circuits above includes a pull-up transistor and a pull-down transistor, and The pull-up transistor includes a gate electrode connected to a first control node, a first electrode to which the clock signal is applied, and a second electrode connected to an output node. The above pull-down transistor comprises a gate driving unit including a gate electrode connected to a second control node, a first electrode connected to an output node, and a second electrode to which a high potential voltage is applied.
A pixel array having a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits arranged therein; A data driving unit that outputs data voltage to the above plurality of data lines; and It includes a gate driver that outputs a gate signal to the above-mentioned plurality of gate lines, and The gate driver above includes a plurality of signal transmission units that are dependently connected via a carry line to which a carry signal is applied from a previous signal transmission unit and output a gate signal according to a clock signal. The nth (n is a positive integer) signal transmission unit, A first output circuit that outputs a carry signal based on a carry signal from a previous signal transmission unit and the clock signal; A selection circuit that receives a carry signal output from the first output circuit and selectively transmits the received carry signal according to the voltage level of the selected data voltage; and A display device comprising a second output circuit that outputs a gate signal based on a carry signal transmitted from the selection circuit and the clock signal.
In Paragraph 10, The above selection circuit is, When the voltage level of the above-mentioned selected data voltage is the gate-on voltage level, the above-mentioned carry signal is output, and A display device that does not transmit the above carry signal when the gate-off voltage level is at the above-mentioned voltage level.
In Paragraph 10, The above selection circuit is, A first transistor comprising a gate electrode to which a selection signal is applied, a first electrode to which the selection data voltage is applied, and a second electrode connected to a first node, A second transistor comprising a gate electrode connected to the first node, a first electrode to which the carry signal is applied, and a second electrode connected to an output node; and A display device comprising a gate electrode connected to the first node, a first electrode connected to the output node, and a third transistor having a second electrode to which a low potential voltage is applied.
In Paragraph 12, A display device in which the second and third transistors are different transistors among a P-channel transistor and an n-channel transistor.
In Paragraph 12, A display device further comprising a capacitor connected between the first node and ground.
In Paragraph 14, The above selection circuit is, When the transistor is turned on by the above selection signal, the selection data voltage is stored in the capacitor, and A gate driver, wherein when the second transistor is turned on by the selected data voltage stored in the capacitor, the carry signal is output through the output node.
In paragraph 15, The above selection circuit is, A gate driver, wherein when the third transistor is turned on by the selected data voltage stored in the capacitor, the low potential voltage is output through the output node.
In Paragraph 12, It further includes a timing controller that controls the operation timing of the data driving unit and the gate driving unit, and The above selection signal is, A display device, which is a signal generated from the timing controller or generated from the gate driver.
In Paragraph 10, Each of the first and second output circuits above includes a pull-up transistor and a pull-down transistor, and The pull-up transistor includes a gate electrode connected to a first control node, a first electrode connected to a low potential voltage, and a second electrode connected to an output node. The above pull-down transistor comprises a gate driving unit including a gate electrode connected to a second control node, a first electrode connected to an output node, and a second electrode connected to a high potential voltage.
In Paragraph 10, Each of the first and second output circuits above includes a pull-up transistor and a pull-down transistor, and The pull-up transistor includes a gate electrode connected to a first control node, a first electrode to which the clock signal is applied, and a second electrode connected to an output node. The above pull-down transistor comprises a gate driving unit including a gate electrode connected to a second control node, a first electrode connected to an output node, and a second electrode to which a high potential voltage is applied.

Description

Gate driver and display device including the same The present invention relates to a gate driving unit and a display device including the same. Electroluminescent display devices are broadly classified into inorganic light-emitting display devices and organic light-emitting display devices depending on the material of the light-emitting layer. Active matrix type organic light-emitting display devices include self-emissive organic light-emitting diodes (OLEDs) and have the advantages of fast response speed, high luminous efficiency, brightness, and viewing angle. In organic light-emitting displays, an organic light-emitting diode (OLED) is formed in each pixel. These organic light-emitting displays not only have fast response speeds and excellent luminous efficiency, brightness, and viewing angles, but also offer superior contrast ratio and color reproduction because they can express black gradations as perfect black. Some of the display devices, such as liquid crystal displays or organic light-emitting displays, include a display panel comprising a plurality of pixels, a driving unit that outputs a driving signal for driving the display panel, and a power supply unit that generates power to be supplied to the display panel or the driving unit. The driving unit includes a gate driving unit that supplies gate signals, such as scan signals and light emission control signals, to the display panel, and a data driving unit that supplies data signals to the display panel. FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. FIG. 2 is a drawing showing a pixel circuit according to an embodiment of the present invention. Figure 3 is a diagram showing the driving timing of the pixel circuit illustrated in Figure 2. FIG. 4 is a diagram showing a shift register of a gate driving unit according to an embodiment. Figure 5 is a diagram showing the driving waveform of the gate driver shown in Figure 4. FIG. 6 is a diagram showing the output circuit configuration of an embodiment illustrated in FIG. 4. Figure 7 is a diagram showing the configuration of the selection circuit illustrated in Figure 4. FIGS. 8a to 8c are drawings for explaining the operating principle of the selection circuit illustrated in FIG. 7. FIG. 9 is a drawing showing a gate driving unit according to one embodiment of the present invention. Figure 10 is a diagram showing the configuration of the output circuit illustrated in Figure 4. FIG. 11 is a drawing showing a gate driving unit according to another embodiment of the present invention. FIG. 12 is a diagram showing the output result of a carry signal according to an embodiment of the present invention. FIG. 13 is a diagram showing the gate signal output result according to an embodiment of the present invention. The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as 'includes,' 'have,' 'consists of,' etc. are used in this specification, other parts may be added unless 'only' is used. Where a component is expressed in the singular, it includes cases where it includes the plural unless specifically stated otherwise. In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement. In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on top of,' 'above,' 'below,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used. In the description of the embodiments, terms such as "first," "second," etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical sc