KR-20260063721-A - DISPLAY APPARATUS

Abstract

Embodiments of the present disclosure relate to a display device, and more specifically, include a substrate, a first planarization layer disposed on the substrate, a conductive pattern positioned on the first planarization layer and spaced apart from each other, a barrier layer disposed on the conductive pattern and the first planarization layer such that it is not disposed on at least a portion of the upper surface of the conductive pattern, and a second planarization layer disposed on the conductive pattern and the barrier layer, thereby providing a display device capable of low power consumption by improving the flatness of the pixel electrode and the occurrence of outgassing of the planarization layer.

Inventors

• 이은혜
• 홍기상
• 임현철

Assignees

• 엘지디스플레이 주식회사

Dates

Publication Date

20260507

Application Date

20241031

Claims (20)

1. Substrate; A first planarization layer disposed on the above substrate; A conductive pattern positioned on the first planarization layer and spaced apart from each other; A barrier layer disposed on the conductive pattern and the first flattening layer such that it is not disposed on at least a portion of the upper surface of the conductive pattern; and It includes a second planarization layer disposed on the conductive pattern and the barrier layer, and The above barrier layer is a display device comprising through holes disposed between the conductive patterns.
2. In paragraph 1, The first flattening layer and the second flattening layer are in contact with each other at the through hole.
3. In paragraph 1, It includes a bank located on the second flattening layer and having an opening disposed therein, The above opening is a display device that overlaps with at least a portion of the conductive pattern.
4. In paragraph 3, The above through hole is a display device not placed in the area overlapping with the above opening.
5. In paragraph 3, The above opening includes a first opening and a second opening, and The above conductive pattern includes a data line that transmits a data voltage and a driving voltage line that transmits a high potential driving voltage, and The first opening is positioned to overlap with at least a portion of the data line, and The second opening is a display device positioned to overlap with at least a portion of the driving voltage line.
6. In paragraph 1, The barrier layer is positioned to be in contact with the side of the conductive pattern, and The second planarization layer is a display device in contact with the upper surface of the conductive pattern.
7. In paragraph 1, The barrier layer is in contact with the lower side of the conductive pattern and is spaced apart from the upper side of the conductive pattern. The above second planarization layer is a display device in contact with the upper surface and side upper surface of the conductive pattern.
8. In paragraph 1, The barrier layer is spaced apart from the conductive pattern, and The second planarization layer is a display device in contact with the upper surface and side surface of the conductive pattern.
9. In paragraph 1, The first planarization layer and the second planarization layer comprise an organic insulating material, The above barrier layer is a display device comprising an inorganic insulating material.
10. In paragraph 5, The above conductive pattern further includes a relay electrode, and The above relay electrode is a display device arranged to overlap with the contact hole of the first flattening layer.
11. In Paragraph 10, It further includes a transistor located on the above substrate, and The above transistor includes a source electrode, a drain electrode, an active layer, and a gate electrode positioned overlapping the active layer, and The above relay electrode is a display device electrically connected to the source electrode through the contact hole of the first planarization layer.
12. In Paragraph 11, It further includes a light-emitting element located on the second planarization layer, and The above light-emitting element is, Pixel electrode disposed on the second planarization layer; An intermediate layer disposed on the pixel electrode; and It includes a common electrode disposed on the intermediate layer above, and A display device in which the pixel electrode is electrically connected to the relay electrode through the contact hole of the second planarization layer.
13. In paragraph 1, A display device disposed on the first flattening layer such that the barrier layer is not disposed over the entire upper surface of the conductive pattern.
14. Substrate; A first planarization layer disposed on the above substrate; A conductive pattern positioned on the first planarization layer and arranged in a first direction; A barrier layer disposed on the conductive pattern and the first planarization layer; A second planarization layer disposed on the conductive pattern and the barrier layer; A pixel electrode disposed on the second planarization layer; and A bank disposed on the pixel electrode and including an opening that exposes a portion of the upper surface of the pixel electrode; comprising The barrier layer includes an open region in which the barrier layer is not disposed on at least a portion of the upper surface of the conductive pattern, and A display device in which the above-mentioned open area overlaps with at least a portion of the pixel electrode.
15. In Paragraph 14, The above open area is a display device that corresponds to the pixel electrode.
16. In Paragraph 14, The above open area is a display device that is an area corresponding to the above opening.
17. In Paragraph 14, The second planarization layer is a display device disposed on the conductive pattern in the open area.
18. In Paragraph 14, The above conductive pattern is spaced apart in a second direction orthogonal to the first direction, and The barrier layer includes through holes disposed between the conductive patterns, and The first flattening layer and the second flattening layer are in contact with each other at the through hole.
19. Substrate; A first planarization layer disposed on the above substrate; A conductive pattern positioned on the first planarization layer, extending in a first direction and spaced apart in a second direction orthogonal to the first direction; A barrier layer disposed on the conductive pattern and the first planarization layer; A second planarization layer disposed on the conductive pattern and the barrier layer; and It includes a light-emitting region arranged in overlap with the above conductive pattern, and The barrier layer includes an open region in which the barrier layer is not disposed on at least a portion of the upper surface of the conductive pattern, and A display device in which the above-mentioned open area overlaps with at least a portion of the above-mentioned light-emitting area.
20. In Paragraph 19, The barrier layer includes through holes disposed between the conductive patterns, and The first flattening layer and the second flattening layer are in contact with each other at the through hole.

Description

Display apparatus The embodiments of the present disclosure relate to a display device. As the information society develops, the demand for display devices that display images is increasing, and various types of display devices, such as liquid crystal displays and light-emitting displays, are being utilized. A light-emitting display device includes a light-emitting element that emits light in a display area, and the light-emitting element includes an anode, a light-emitting layer, and a cathode. The light-emitting element must be formed on a flat surface so that light can be emitted uniformly and evenly. Various components, including wiring and driving elements that supply signals and voltage, are formed on the lower part of the light-emitting element, so the surface is not flat and has a step. A planarization layer made of organic material may be disposed to stably place the light-emitting element on the planarized surface and to planarize the lower part of the light-emitting element. FIG. 1 is a system configuration diagram of a display device according to embodiments of the present disclosure. FIG. 2 shows a display panel according to embodiments of the present disclosure. FIG. 3 is a cross-sectional view of a display panel according to embodiments of the present disclosure. FIG. 4 is a simplified plan view illustrating a plurality of subpixels arranged in a display area of a display panel according to embodiments of the present disclosure. FIGS. 5 to 7 are exemplary cross-sectional views showing a cross-section cut along line AB of FIG. 4. FIGS. 8 and 9 are exemplary cross-sectional views showing a cross section cut along the CD line of FIG. 4. Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions may obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise. Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by such terms. In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another. In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used. Meanwhile, where numerical values or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.). Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings. FIG. 1 is a system configuration diagram of a display device (100) according to embodiments of the present disclosure. Referring to FIG. 1, a display device (100) according to embodiments of the present disclosure may include a display panel (110) and a display driving circuit as components for displaying an image. The display driving circuit may include a data driving circuit (120), a gate driving circuit (130), and a controller (140), etc., as a circuit for driving the display panel (110). The display panel (110) may include a substrate (111) and a plurality of subpixels (SP) disposed on the substrate (111). The substrate (111) may include a display area (DA) capable of displaying an image and a non-display area (NDA) located at the outer edge of the display area (DA). The display area (DA) may also be referred to as the active area, and a plur