KR-20260063765-A - SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

Abstract

A semiconductor memory device and an electronic system including the same are provided. The semiconductor memory device comprises a substrate, a stacked structure including gate electrodes and insulating layers alternately stacked on the substrate in a first direction perpendicular to the upper surface of the substrate, a channel structure extending in a first direction through the stacked structure, and a bit line connected to the channel structure through a contact plug on the channel structure, wherein the channel structure includes a core insulating layer, a channel layer on the side of the core insulating layer, a channel insulating layer extending between the channel layer and the gate electrodes, and a channel pad in contact with the channel layer on the core insulating layer, and the channel pad includes a first pad layer having a material of a first conductivity type and a second pad layer having a material of a second conductivity type different from the first conductivity type on the first pad layer in a first direction, and the outermost surface of the second pad layer is in contact with the channel insulating layer.

Inventors

• 김좌섭
• 김형섭
• 이용규
• 전종욱

Assignees

• 삼성전자주식회사
• 성균관대학교산학협력단

Dates

Publication Date

20260507

Application Date

20241031

Claims (20)

1. Substrate; A stacked structure comprising gate electrodes and insulating layers alternately stacked on the substrate in a first direction perpendicular to the upper surface of the substrate; A channel structure penetrating the above-mentioned laminated structure and extending in the first direction; and It includes a bit line connected to the channel structure through a contact plug on the channel structure, The channel structure comprises a core insulating layer, a channel layer on the side of the core insulating layer, a channel insulating layer extending between the channel layer and the gate electrodes, and a channel pad on the core insulating layer in contact with the channel layer. The above channel pad is, A first pad layer comprising a first conductive type material and A second pad layer comprising a material having a second conductivity type different from the first conductivity type, on the first pad layer in the first direction, and A semiconductor memory device in which the outermost surface of the second pad layer is in contact with the channel insulating layer.
2. In Article 1, A semiconductor memory device in which the side of the first pad layer is not in contact with the second pad layer.
3. In Article 1, A semiconductor memory device in which the width of the first pad layer is smaller than the width of the second pad layer.
4. In Article 1, The above channel layer is in direct contact with the side of the first pad layer, and A semiconductor memory device in which the lower surface of the first pad layer and the core insulating layer are in direct contact.
5. In Article 1, The above first and second pad layers are in direct contact with a semiconductor memory device.
6. In Article 1, The above channel pad is, Between the first and second pad layers, a first semiconductor material layer that is not doped with impurities is further included, A semiconductor memory device in which the upper surface of the first pad layer and the lower surface of the second pad layer are in contact with the first semiconductor material layer, respectively.
7. In Article 1, The above channel pad is, Between the channel layer and the first pad layer, a second semiconductor material layer that is not doped with impurities is further included, A semiconductor memory device in which the second semiconductor material layer is formed along a portion of the side of the channel layer and the upper surface of the core insulating layer.
8. In Article 7, A semiconductor memory device in which, in the first direction, the upper surface of the second semiconductor material layer is located at the same level as the upper surface of the channel layer.
9. In Article 1, The second pad layer is a semiconductor memory device that overlaps at least partially with the uppermost gate electrode among the gate electrodes.
10. In Article 1, A semiconductor memory device in which the second pad layer covers a part of the sidewall and the upper surface of the core insulating layer.
11. In Article 1, The above second pad layer is a T-shaped semiconductor memory device.
12. In Article 1, The first pad layer comprises polysilicon doped with P-type impurities, and The above second pad layer is a semiconductor memory device comprising polysilicon doped with N-type impurities.
13. In Article 1, The first pad layer comprises polysilicon doped with N-type impurities, and The above second pad layer is a semiconductor memory device comprising polysilicon doped with P-type impurities.
14. Substrate; A stacked structure comprising gate electrodes and insulating layers alternately stacked in a vertical direction on the above substrate; A channel structure penetrating the above-mentioned stacked structure and extending in the above-mentioned vertical direction; and It includes a bit line connected to the channel structure through a contact plug on the channel structure, The channel structure comprises a core insulating layer, a channel layer on the side of the core insulating layer, a channel insulating layer extending between the channel layer and the gate electrodes, and a channel pad on the core insulating layer in contact with the channel layer. The above channel pad is, A first pad layer comprising polysilicon doped with impurities of the first conductivity type, A second pad layer comprising polysilicon doped with impurities of a second conductivity type different from the first conductivity type on the first pad layer, and Between the first and second pad layers, a first polysilicon layer not doped with impurities is included, and A semiconductor memory device in which the side of the first pad layer is not in contact with the second pad layer.
15. In Paragraph 14, A semiconductor memory device in which the upper surface of the above channel layer is in contact with the first polysilicon layer.
16. In Paragraph 14, A semiconductor memory device in which the upper surface of the above channel layer contacts the above first pad layer.
17. In Paragraph 14, The above channel pad is, A semiconductor memory device further comprising a second polysilicon layer formed between the channel layer and the first pad layer, along a portion of the side of the channel layer and the upper surface of the core insulating layer, and not doped with impurities.
18. In Paragraph 14, The above channel layer extends between the core insulating layer and the channel insulating layer, and The first pad layer extends on the channel layer between the core insulating layer and the channel insulating layer, and The first polysilicon layer extends on the first pad layer between the core insulating layer and the channel insulating layer, and A semiconductor memory device in which, in the above vertical direction, the upper surface of the core insulating layer is located at a higher level than the upper surface of the first polysilicon layer.
19. In Paragraph 14, The above channel layer extends between the core insulating layer and the channel insulating layer, and The first pad layer extends on the channel layer between the core insulating layer and the channel insulating layer, and The first polysilicon layer extends on the first pad layer between the core insulating layer and the channel insulating layer, and A semiconductor memory device in which, in the above vertical direction, the upper surface of the core insulating layer is located at a lower level than the upper surface of the first polysilicon layer.
20. A peripheral circuit structure including circuit elements on a semiconductor substrate; A pattern structure comprising, on the above peripheral circuit structure, a lower pattern layer, an intermediate pattern layer disposed on the lower pattern layer and containing an impurity of a first conductivity type, and an upper pattern layer on the intermediate pattern layer; A stacked structure comprising gate electrodes and insulating layers alternately stacked in a vertical direction on the above pattern structure; A channel structure penetrating the above-mentioned stacked structure and extending in the above-mentioned vertical direction; and It includes a bit line connected to the channel structure through a contact plug on the channel structure, The channel structure comprises a core insulating layer, a channel layer on the side of the core insulating layer, a channel insulating layer extending between the channel layer and the gate electrodes, and a channel pad on the core insulating layer in contact with the channel layer. The above channel pad is, A first pad layer containing impurities of a second conductivity type different from the first conductivity type, A second pad layer comprising impurities of the first conductivity type, on the first pad layer in the vertical direction above, and Between the first and second pad layers, a first polysilicon layer not doped with impurities is included, and A semiconductor memory device in which the outermost surface of the second pad layer is in contact with the channel insulating layer.

Description

Semiconductor memory device and electronic system including the same The present invention relates to a semiconductor memory device and an electronic system including the same. To meet the superior performance and low prices demanded by consumers, it is necessary to increase the integration density of semiconductor memory devices. Since integration density is a critical factor in determining product prices for semiconductor memory devices, particularly increased integration density is required. Meanwhile, in the case of two-dimensional or planar semiconductor memory devices, the integration density is primarily determined by the area occupied by a unit memory cell, and thus is significantly influenced by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for pattern miniaturization, the integration density of two-dimensional semiconductor memory devices is increasing but remains limited. Accordingly, three-dimensional semiconductor memory devices equipped with memory cells arranged in three dimensions are being proposed. FIG. 1 is an exemplary block diagram for illustrating a semiconductor memory device according to some embodiments. FIG. 2 is a schematic layout diagram for illustrating a semiconductor memory device according to some embodiments. FIG. 3 is a drawing for explaining a semiconductor memory device according to some embodiments, and is a cross-sectional view taken along I-I' of FIG. 2. Figure 4 is an enlarged view of area A1 in Figure 3. FIG. 5 is a drawing for explaining a semiconductor memory device according to some embodiments, and is a drawing corresponding to FIG. 4. FIG. 6 is a drawing for explaining a semiconductor memory device according to some embodiments, and is a drawing corresponding to FIG. 4. FIG. 7 is a drawing for explaining a semiconductor memory device according to some embodiments, and is a drawing corresponding to FIG. 4. FIG. 8 is a drawing for explaining a semiconductor memory device according to some embodiments, and is a drawing corresponding to FIG. 4. FIG. 9 is another exemplary cross-sectional view for illustrating a semiconductor memory device according to some embodiments. Figure 10 is an enlarged view of area A2 in Figure 9. FIG. 11 is a drawing for explaining a semiconductor memory device according to some embodiments, and is a drawing corresponding to FIG. 10. FIG. 12 is a drawing for explaining a semiconductor memory device according to some embodiments, and is a drawing corresponding to FIG. 10. FIG. 13 is another exemplary cross-sectional view for illustrating a semiconductor memory device according to some embodiments. Figure 14 is an enlarged view of area A3 of Figure 13. FIG. 15 is another exemplary cross-sectional view for illustrating a semiconductor memory device according to some embodiments. Figure 16 is an enlarged view of area A4 of Figure 15. FIG. 17 is another exemplary cross-sectional view for illustrating a semiconductor memory device according to some embodiments. Figure 18 is an enlarged view of area A5 of Figure 17. FIG. 19 is another exemplary cross-sectional view for illustrating a semiconductor memory device according to some embodiments. FIG. 20 is another exemplary cross-sectional view for illustrating a semiconductor memory device according to some embodiments. FIGS. 21 to 28 are intermediate drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments. FIGS. 29 to 33 are other intermediate drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments. FIGS. 34 to 35 are other intermediate drawings for illustrating a method of manufacturing a semiconductor memory device according to some embodiments. FIGS. 36 and 37 are other intermediate drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments. FIGS. 38 to 45 are other intermediate drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments. FIGS. 46 to 51 are other intermediate drawings for illustrating a method of manufacturing a semiconductor memory device according to some embodiments. FIGS. 52 to 54 are other intermediate drawings for explaining a method of manufacturing a semiconductor memory device according to some embodiments. FIGS. 55 to 61 are other intermediate drawings for illustrating a method of manufacturing a semiconductor memory device according to some embodiments. FIG. 62 is an exemplary block diagram for illustrating an electronic system according to some embodiments. FIG. 63 is an exemplary perspective view for illustrating an electronic system according to some embodiments. FIG. 64 is a schematic cross-sectional view taken along the line II-II' of FIG. 63. FIG. 1 is an exemplary block diagram for illustrating a semiconductor memory device according to some embodiments. Referring to FIG. 1, a semiconductor memory devic