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KR-20260063769-A - SEMICONDUCTOR DEVICES

KR20260063769AKR 20260063769 AKR20260063769 AKR 20260063769AKR-20260063769-A

Abstract

A semiconductor device may include: channels that are each extended in a first direction parallel to the upper surface of the substrate and spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; gate structures that are each extended in a second direction parallel to the upper surface of the substrate and intersecting the first direction, and each surround a portion of the channels; a bit line that is extended in the vertical direction and disposed on one side of the channels in the first direction and electrically connected to them; ohmic contact structures having first ohmic contacts disposed on the other side of the channels in the first direction and second ohmic contacts protruding from the surface of each of the first ohmic contacts; and a capacitor structure having first capacitor electrodes disposed on the surface of the ohmic contact structures, a dielectric pattern disposed on the outer wall of the first capacitor electrodes, and a second capacitor electrode disposed on the outer wall of the dielectric pattern.

Inventors

  • 임한진

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20241031

Claims (10)

  1. Channels each extending in a first direction parallel to the upper surface of the substrate and spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; Gate structures that each extend in a second direction parallel to the upper surface of the substrate and intersect the first direction, and each surround a portion of the channels; A bit line extending in the above vertical direction and positioned on one side of the above channels in the first direction and electrically connected to them; Ohmic contact structures having first ohmic contacts disposed on the other side of the channels in the first direction, and second ohmic contacts protruding from the surface of each of the first ohmic contacts; and A semiconductor device comprising a capacitor structure having first capacitor electrodes disposed on the surfaces of the ohmic contact structures, a dielectric pattern disposed along the outer wall of the first capacitor electrodes, and a second capacitor electrode disposed along the outer wall of the dielectric pattern.
  2. A semiconductor device according to claim 1, wherein each of the second ohmic contacts is hemispherical grain silicon (HSG-Si).
  3. A semiconductor device according to claim 1, wherein the second ohmic contacts are spaced apart from each other along the upper and lower surfaces of each of the first ohmic contacts and the side walls of the first and second directions.
  4. A semiconductor device according to claim 1, wherein the dielectric pattern portion and the second capacitor electrode portion arranged along the outer wall of the first capacitor electrodes are curved in correspondence with the surface profile of the ohmic contact structures.
  5. In paragraph 1, A separation structure disposed between the above gate structures; and A semiconductor device further comprising an etch stop film covering the sidewall in the first direction of the separation structure adjacent to the capacitor structure.
  6. In claim 5, the dielectric pattern is arranged along the surface of the first capacitor electrodes and the sidewall of the etch stop film in a semiconductor device.
  7. A semiconductor device according to claim 6, wherein the separation structure comprises silicon oxide, silicon nitride, or a combination thereof, and the etch stop layer comprises hafnium oxide, zirconium oxide, tantalum oxide, niobium oxide, titanium oxide, lanthanum oxide, or a combination thereof.
  8. A semiconductor device according to claim 1, wherein the ohmic contact structures are disposed on the upper and lower surfaces and side walls of the channels.
  9. In claim 1, the ohmic cotect structures are semiconductor devices extending in the first direction from the sidewall on the other side of the channels, respectively.
  10. In claim 1, the ohmic contact structures comprise a semiconductor device comprising a semiconductor material doped with n-type impurities or a semiconductor material doped with p-type impurities.

Description

Semiconductor Devices The present invention relates to a semiconductor device. More specifically, the present invention relates to a three-dimensional DRAM (3D-DRAM) device. A DRAM device may include word lines, bit lines, channels, and capacitors, and research is needed on technology to improve integration density by efficiently arranging them. FIGS. 1 to 6 are perspective views, horizontal cross-sectional views, and vertical cross-sectional views for illustrating a semiconductor device according to exemplary embodiments. FIGS. 7 to 48 are vertical and horizontal cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. FIGS. 49 and FIGS. 50 are vertical cross-sectional views for illustrating a semiconductor device according to exemplary embodiments. Hereinafter, a semiconductor device and a method for manufacturing the same according to preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Where materials, layers (films), regions, pads, electrodes, patterns, structures, or processes are referred to as "first," "second," and/or "third" in this specification, it is not intended to limit these components but merely to distinguish each material, layer (film), region, electrode, pad, pattern, structure, and process. Accordingly, "first," "second," and/or "third" may be used selectively or interchangeably for each material, layer (film), region, electrode, pad, pattern, structure, and process. In the following, two directions that intersect each other among the horizontal directions parallel to the upper surface of the substrate are defined as the first and second directions (D1, D2), respectively, and a vertical direction perpendicular to the upper surface of the substrate is defined as the third direction (D3). In exemplary embodiments, the first and second directions (D1, D2) may be orthogonal to each other. Meanwhile, each of the first to third directions (D1, D2, D3) may include not only the directions shown in the drawings but also directions opposite thereto. [Example] FIGS. 1 to 6 are perspective views, horizontal cross-sectional views, and vertical cross-sectional views for illustrating a semiconductor device according to exemplary embodiments. Specifically, FIG. 1 is a schematic diagram showing only the main parts of the semiconductor device in a simplified manner as a perspective view of FIGS. 2 to 4; FIG. 2 is a horizontal cross-sectional view at height H of FIGS. 3 and 4; FIGS. 3 and 4 are vertical cross-sectional views cut along the A-A' and C-C' lines of FIG. 2, respectively; FIG. 5 is an enlarged cross-sectional view of the X region of FIG. 4; and FIG. 6 is a vertical cross-sectional view of the Y region cut along the D-D' line of FIG. 5. Referring to FIGS. 1 through 6, the semiconductor device may include a memory cell region in which memory cells are arranged, and a peripheral circuit region in which circuit patterns for applying electrical signals to the memory cells are arranged. The memory cell region may include memory cell block regions, each comprising a plurality of memory cells, and the memory cell block regions may be arranged along first and second directions (D1, D2) within the memory cell region and separated from one another by a first separation structure (180). The first separation structure (180) may be in contact with the upper surface of the memory cell region of the substrate (100) and may have, for example, a grid shape when viewed from above. In one embodiment, the first separation structure (180) may include a first separation pattern (160) and a second separation pattern (170) covering the sidewalls and bottom surface thereof. The first separation pattern (160) may include an insulating nitride, for example, silicon nitride, and the second separation pattern (170) may include an oxide, for example, silicon oxide. Each of the above memory cell block regions may include first and second regions (I, II), the first region (I) may be a memory cell array region in which a memory cell array including the memory cells is disposed, and the second region (II) may be a pad region or an extension region in which contact plugs for transmitting electrical signals to the memory cell array or conductive pads in contact therewith are disposed. In exemplary embodiments, the second region (II) may be positioned on one or both sides toward the first direction (D1) of the first region (I). FIG. 2 illustrates a portion of the memory cell block region, namely a portion of each of the first and second regions (I, II). The semiconductor device may include first channels (125), first gate structures, bit lines (440), ohmic contact structures (587), etch stop layer (515), capacitor structures, conductive pads (430), and first to third contact plugs (612, 614, 616) disposed on a substrate (100). Additionally, the semiconductor device may further include a dummy bit line (4