KR-20260063895-A - SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Abstract

According to embodiments of the present disclosure, a semiconductor package may include a semiconductor chip, a bonding wire having one side in contact with the upper surface of the semiconductor chip, a landing pad having the other side in contact with the bonding wire and facing the upper surface of the semiconductor chip, a coating layer having a hole disposed between the landing pad and the semiconductor chip and surrounding the side of the bonding wire, and an encapsulation layer surrounding the coating layer.

Inventors

• 장헌용
• 정영훈

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260507

Application Date

20241031

Claims (20)

1. semiconductor chip; A bonding wire having one side in contact with the upper surface of the semiconductor chip; A landing pad that contacts the other side of the bonding wire and faces the upper surface of the semiconductor chip; A coating layer disposed between the landing pad and the semiconductor chip, surrounding the side of the bonding wire, and including a hole; and An encapsulation layer surrounding the above coating layer; A semiconductor package including
2. In paragraph 1, The above-mentioned encapsulation layer is a semiconductor package that fills the inside of the above-mentioned hole.
3. In paragraph 1, A semiconductor package in which the above-mentioned encapsulation layer contacts the side of the bonding wire through the above-mentioned hole.
4. In paragraph 1, The above hole is a semiconductor package extending from the outer surface of the coating layer to the side of the bonding wire.
5. In paragraph 1, A semiconductor package in which the length of the coating layer is smaller than the length of the bonding wire in a direction perpendicular to the upper surface of the semiconductor chip.
6. In paragraph 1, The lower surface of the coating layer has a first width, and the upper surface of the coating layer has a second width, and A semiconductor package in which the first width is larger than the second width.
7. In paragraph 1, The above bonding wire includes first and second bonding wires connected to different semiconductor chips, and A semiconductor package in which the coating layer surrounding the side of the first bonding wire is spaced apart from the coating layer surrounding the side of the second bonding wire.
8. In paragraph 1, The above coating layer is a semiconductor package corresponding to each of the bonding wires.
9. In paragraph 1, The above-mentioned encapsulation layer is a semiconductor package that covers the upper surface of the semiconductor chip.
10. First semiconductor chip; A second semiconductor chip located on the first semiconductor chip; A first bonding wire connected to the first semiconductor chip; A second bonding wire connected to the second semiconductor chip; A first coating layer surrounding the side of the first bonding wire and including a first hole; A second coating layer surrounding the side of the second bonding wire, including a second hole, and spaced apart from the first coating layer; and A sealing layer surrounding the first coating layer and the second coating layer, and filling the interior of the first hole and the second hole; A semiconductor package including
11. In Paragraph 10, A semiconductor package in which the above-mentioned encapsulation layer contacts the sides of the first bonding wire and the second bonding wire, respectively, through the first hole and the second hole.
12. In Paragraph 10, A semiconductor package in which, in a direction perpendicular to the upper surface of the first semiconductor chip or the second semiconductor chip, the length of the first coating layer and the second coating layer is smaller than the length of the first or second bonding wire.
13. In Paragraph 10, A semiconductor package in which, in a direction perpendicular to the upper surface of the first semiconductor chip or the second semiconductor chip, the length of the first coating layer is greater than the length of the second coating layer.
14. In Paragraph 10, The second semiconductor chip is a semiconductor package stacked directly on top of the first semiconductor chip.
15. In Paragraph 10, The lower surface of the first coating layer has a first width, and the upper surface of the first coating layer has a second width, and A semiconductor package in which the first width is larger than the second width.
16. In Paragraph 10, The above-mentioned encapsulation layer is a semiconductor package covering the upper surface of the first and second semiconductor chips.
17. A step of connecting one side of a bonding wire to a semiconductor chip and aligning the bonding wire in a direction perpendicular to the upper surface of the semiconductor chip; A step of forming a coating layer surrounding the side of the bonding wire and including a hole; and A step of forming a sealing layer to surround the sides of the coating layer and fill the interior of the hole; A method for manufacturing a semiconductor package including
18. In Paragraph 17, A method for manufacturing a semiconductor package in which the above-described encapsulation layer contacts the side of the bonding wire through the above-described hole.
19. In Paragraph 17, The above bonding wire includes first and second bonding wires spaced apart from each other, and The step of forming the coating layer above is, A step of forming a first coating layer surrounding the side of the first bonding wire and including a first hole; and A method for manufacturing a semiconductor package comprising the step of forming a second coating layer containing a second hole surrounding the side of the second bonding wire.
20. In Paragraph 19, A method for manufacturing a semiconductor package in which the first coating layer and the second coating layer are spaced apart from each other.

Description

Semiconductor Package and Manufacturing Method Thereof The embodiments of the present disclosure relate to a semiconductor package and a method for manufacturing the same. Due to characteristics such as miniaturization, multifunctionality, and/or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. As the electronics industry advances, semiconductor devices are becoming increasingly highly integrated. To achieve this high integration, stacking methods for semiconductor chips are being used. However, the technology for forming input/output wiring on semiconductor chips during stacking is facing various technical limitations. FIG. 1 is a drawing showing an example of a cross-sectional structure of a semiconductor package according to embodiments of the present disclosure. Figure 2 is an enlarged view of 10 in Figure 1. Figures 3 and 4 are drawings showing the three-dimensional structure and planar structure of a part of Figure 2. Figure 5 is a drawing showing another example of Figure 2. FIG. 6 is a drawing showing an example of a planar structure of a semiconductor package according to embodiments of the present disclosure. FIG. 7 is a drawing showing another example of a cross-sectional structure of a semiconductor package according to embodiments of the present disclosure. FIGS. 8 to 14 are drawings illustrating examples of a method for manufacturing a semiconductor package according to embodiments of the present disclosure. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the attached drawings, two directions parallel to the upper surface of the semiconductor chip are defined as the first direction (FD) and the second direction (SD), respectively, and a direction protruding perpendicularly from the upper surface of the semiconductor chip is defined as the third direction (VD). The first direction (FD) and the second direction (SD) may be substantially perpendicular to each other. The third direction (VD) is a direction perpendicular to the first direction (FD) and the second direction (SD). In the following specification, "perpendicular" or "perpendicular direction" will be used with substantially the same meaning as the third direction (VD). In the drawings, directions indicated by arrows and opposite directions represent the same direction. FIG. 1 is a drawing showing an example of a cross-sectional structure of a semiconductor package according to embodiments of the present disclosure. FIG. 2 is an enlarged view of 10 of FIG. 1. FIG. 6 is a drawing showing an example of a planar structure of a semiconductor package according to embodiments of the present disclosure. FIG. 1 may be a cross-sectional view of the section along the cutting line I-I' of FIG. 6. Referring to FIGS. 1 and 6, a semiconductor package according to embodiments of the present disclosure includes semiconductor chips (101, 102, 103, 104), connecting wires (121, 122, 123, 124), a coating layer (131, 132, 133), an encapsulation layer (150), an adhesive layer (160), a rewiring layer (180), and an external connection terminal (190). The semiconductor chips (101, 102, 103, 104) include a first semiconductor chip (101), a second semiconductor chip (102), a third semiconductor chip (103), and a fourth semiconductor chip (104). The semiconductor chips (101, 102, 103, 104) may include memory such as volatile memory, non-volatile memory, or a combination thereof. Each of the semiconductor chips (101, 102, 103, 104) may include Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Flash Memory, Magnetoresistive Random Access Memory (MRAM), Phase-change Random Access Memory (PRAM), Ferroelectric Random Access Memory (FRAM), Resistive Random Access Memory (RRAM), or a combination thereof. In one embodiment, at least one of the semiconductor chips (101, 102, 103, 104) may be a logic chip such as a controller. The connecting wires (121, 122, 123, 124) include a first connecting wire (121), a second connecting wire (122), a third connecting wire (123), and a fourth connecting wire (124). The coating layer (131, 132, 133) includes a first coating layer (131), a second coating layer (132), and a third coating layer (133). The redistribution layer (180) includes a landing pad (182), an internal wiring (183), an upper pad (184), and an insulating layer (181). The second semiconductor chip (102) may be offset stacked on the first semiconductor chip (101) in a first direction (FD). The third semiconductor chip (103) may be offset stacked on the second semiconductor chip (102) in a first direction (FD). The fourth semiconductor chip (104) may be offset stacked on the third semiconductor chip (103) in a first direction (FD). The fourth semiconductor chip (104) may be offset stacked in a direction opposite to the direction in which the third semiconductor chip (103) is offset stacked. The first se