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KR-20260064064-A - DISPLAY APPARARTUS

KR20260064064AKR 20260064064 AKR20260064064 AKR 20260064064AKR-20260064064-A

Abstract

A display device according to various embodiments of the present specification comprises a plurality of pixel lines including an m-th pixel line and an m+1-th pixel line, a plurality of data lines including a first data line connected to a plurality of subpixel circuits disposed on the m-th pixel line and a second data line connected to a plurality of subpixel circuits disposed on the m+1-th pixel line, wherein m is a natural number, the color implemented by the subpixel circuit connected to the first data line is the same as the color implemented by the subpixel circuit connected to the second data line, and the pixel column in which the subpixel circuit connected to the first data line is disposed may be the same as the pixel column in which the subpixel circuit connected to the second data line is disposed.

Inventors

  • 홍상표
  • 백승한
  • 안현진

Assignees

  • 엘지디스플레이 주식회사

Dates

Publication Date
20260507
Application Date
20241031

Claims (20)

  1. A plurality of pixel lines including an m-th pixel line and an m+1-th pixel line, each including a plurality of subpixel circuits; and It includes a plurality of data lines, comprising a first data line connected to a plurality of subpixel circuits arranged in the m-th pixel line and a second data line connected to a plurality of subpixel circuits arranged in the m+1-th pixel line. m is a natural number, and The color implemented by the subpixel circuit connected to the first data line is the same as the color implemented by the subpixel circuit connected to the second data line, and A display device in which a pixel column having a subpixel circuit connected to the first data line is the same as a pixel column having a subpixel circuit connected to the second data line.
  2. In Article 1, It further includes a plurality of scan lines arranged to intersect with the plurality of data lines mentioned above, and The above plurality of scan lines includes the m-th second gate line and the m+1-th second gate line, and The m-th pixel line receives the m-th second scan signal from the m-th second gate line, and A display device in which the m+1th pixel line receives the m+1th second scan signal from the m+1th second gate line.
  3. In Article 1, It further includes a plurality of pixel columns including an n-th pixel column and an n+1-th pixel column, each including a plurality of subpixel circuits, and n is a natural number, a display device.
  4. In Paragraph 3, Drive IC; A plurality of demultiplexer lines disposed between the above drive IC and the plurality of subpixel circuits; and A display device further comprising a plurality of demultiplexer transistors, each comprising a gate electrode connected to the plurality of demultiplexer lines.
  5. In Paragraph 4, The above demultiplexer line includes a first demultiplexer line, a second demultiplexer line, a third demultiplexer line, and a fourth demultiplexer line, and The above plurality of demultiplexer transistors are, A first demultiplexer transistor comprising a gate electrode connected to the first demultiplexer line; A second demultiplexer transistor comprising a gate electrode connected to the second demultiplexer line; A third demultiplexer transistor comprising a gate electrode connected to the third demultiplexer line; and A display device comprising a fourth demultiplexer transistor including a gate electrode connected to the fourth demultiplexer line.
  6. In Article 5, The first demultiplexer transistor includes a first electrode connected to the first data line and a second electrode connected to the drive IC, and The second demultiplexer transistor includes a first electrode connected to the second data line and a second electrode connected to the drive IC, and The third demultiplexer transistor includes a first electrode connected to the first data line and a second electrode connected to the drive IC, and A display device comprising a first electrode connected to the second data line and a second electrode connected to the drive IC, wherein the fourth demultiplexer transistor comprises the above-mentioned first electrode connected to the second data line.
  7. In Article 6, The above first data line is, A first-1 data line connected to a plurality of subpixel circuits arranged in the nth pixel column; and It includes first and second data lines connected to a plurality of subpixel circuits arranged in the n+1th pixel column, and The above second data line is, A second-1 data line connected to a plurality of subpixel circuits arranged in the nth pixel column; and A display device comprising a second-2 data line connected to a plurality of subpixel circuits arranged in the n+1th pixel column.
  8. In Article 7, At least a portion of the above 1-1 data line is connected to the above 1 demultiplexer transistor, and The remaining portion of the above 1-1 data line is connected to the above 3 demultiplexer transistor, and The number of the first-1 data lines connected to the first demultiplexer transistor is, A display device that is different from the number of the first-1 data lines connected to the third demultiplexer transistor.
  9. In Article 8, At least a portion of the first and second data lines is connected to the first demultiplexer transistor, and The remaining portion of the above first- and second data lines is connected to the above third demultiplexer transistor, and The number of the first-1 data lines connected to the first demultiplexer transistor is, A display device having the same number of first and second data lines connected to the third demultiplexer transistor.
  10. In Article 8, The number of the first-1 data lines connected to the third demultiplexer transistor is, A display device having the same number of first- and second data lines connected to the first demultiplexer transistor.
  11. In Article 7, At least a portion of the above 2-1 data line is connected to the above 2 demultiplexer transistor, and The remaining part of the above 2-1 data line is connected to the above 4 demultiplexer transistor, and The number of the 2-1 data lines connected to the 2nd demultiplexer transistor is, A display device that is different from the number of the 2-1 data lines connected to the 4th demultiplexer transistor.
  12. In Article 11, At least a portion of the above 2-2 data line is connected to the above 2 demultiplexer transistor, and The remaining part of the above 2-2 data line is connected to the above 4 demultiplexer transistor, and The number of the 2-1 data lines connected to the 2nd demultiplexer transistor is, A display device having the same number of 2-2 data lines connected to the 4th demultiplexer transistor.
  13. In Article 11, The number of the 2-1 data lines connected to the 4th demultiplexer transistor is, A display device having the same number of data lines as the second-2 connected to the second demultiplexer transistor.
  14. In Article 7, A first capacitor connected to the first data line; and A display device further comprising a second capacitor connected to the second data line.
  15. In Article 5, The above plurality of subpixel circuits, A first subpixel circuit that implements a first color; A second subpixel circuit for implementing a second color; and A display device comprising a third subpixel circuit that implements a third color.
  16. In Article 15, The above demultiplexer line includes a fifth demultiplexer line and a sixth demultiplexer line, and The above plurality of demultiplexer transistors are, A fifth demultiplexer transistor comprising a gate electrode connected to the fifth demultiplexer line; and A display device further comprising a sixth demultiplexer transistor including a gate electrode connected to the sixth demultiplexer line.
  17. In Article 16, The first subpixel circuit is connected to the first demultiplexer transistor and the second demultiplexer transistor, and The second subpixel circuit is connected to the third demultiplexer transistor and the fourth demultiplexer transistor, and A display device in which the third subpixel circuit is connected to the fifth demultiplexer transistor and the sixth demultiplexer transistor.
  18. In Article 16, The first subpixel circuit comprises a first-1 subpixel circuit disposed on the m-th pixel line and a first-2 subpixel circuit disposed on the m+1-th pixel line, and The second subpixel circuit comprises a second-1 subpixel circuit disposed on the m-th pixel line and a second-2 subpixel circuit disposed on the m+1-th pixel line, and A display device comprising a third subpixel circuit, wherein the third subpixel circuit comprises a third-1 subpixel circuit disposed in the m-th pixel line and a third-2 subpixel circuit disposed in the m+1-th pixel line.
  19. In Article 18, The above 1-1 subpixel circuit is connected to the above 1 demultiplexer transistor, and The above first-second subpixel circuit is connected to the above second demultiplexer transistor, and The above 2-1 subpixel circuit is connected to the above 3 demultiplexer transistor, and The above 2-2 subpixel circuit is connected to the above 4 demultiplexer transistor, and The above 3-1 subpixel circuit is connected to the above 5 demultiplexer transistor, and A display device in which the above 3-2 subpixel circuit is connected to the above 6 demultiplexer transistor.
  20. A plurality of pixel lines comprising k pixel lines each including a plurality of subpixel circuits; and It includes a plurality of data lines, each including k data lines connected to the plurality of subpixel circuits mentioned above, and The above k pixel lines are, Includes the m-th pixel line, the m+1-th pixel line, the m+2-th pixel line to the m+(k-1)-th pixel line, and The above k data lines are, It includes a first data line, a second data line, and third to k-th data lines, each connected to the m-th pixel line, the m+1-th pixel line, the m+2-th pixel line, and the m+(k-1)-th pixel line, respectively, and m and k are natural numbers, and The colors implemented by the subpixel circuits connected to the first to kth data lines are all identical to each other, and A display device in which pixel columns having subpixel circuits connected to the first to kth data lines are all identical.

Description

Display device {DISPLAY APPARARTUS} This specification relates to a display device. Electroluminescence displays can be classified into inorganic light-emitting displays and organic light-emitting displays depending on the material of the light-emitting layer. Active matrix type organic light-emitting displays include self-emissive Organic Light Emitting Diodes (OLEDs) and have the advantages of fast response speed, high luminous efficiency, brightness, and high viewing angles. In organic light-emitting displays, OLEDs are formed in each pixel. Organic light-emitting displays not only offer fast response speeds and excellent luminous efficiency, brightness, and viewing angles, but also superior contrast ratio and color reproduction because they can express black gradations as perfect black. Recently, panel structures are being developed to reduce the number of data lines without reducing the number of pixels. Since these display devices have a small number of data lines, the number of output channels of the data driver can be reduced. However, because these display devices must supply data to the pixels through a relatively small number of data lines, problems may arise such as increased driving frequency and increased power consumption. FIG. 1 is a block diagram showing a display device according to one embodiment of the present specification. Figure 2 is a cross-sectional view briefly showing the cross-sectional structure of the display panel illustrated in Figure 1. FIG. 3 is a plan view showing a display panel according to an embodiment of the present specification. Figure 4 is a diagram illustrating the phenomenon where the size of the non-display area increases as the number of drive ICs decreases. FIG. 5 is a cross-sectional view showing a pixel of a display panel according to an embodiment of the present specification. FIG. 6 is a perspective view showing a display device according to an embodiment of the present specification. FIG. 7 is a cross-sectional view taken along I-I' of FIG. 6. FIG. 8 is a perspective view showing a bent appearance of a display device according to an embodiment of the present specification. FIG. 9 is a cross-sectional view taken along II-II' of FIG. 8. FIG. 10 is a schematic diagram showing a shift register of a gate driving unit according to one embodiment of the present specification. FIG. 11 is a circuit diagram showing a pixel circuit according to one embodiment of the present specification. FIG. 12 is a waveform diagram showing gate signals and data voltages applied to the pixel circuit illustrated in FIG. 11. FIGS. 13 to 15 are circuit diagrams showing the operation of the pixel circuit illustrated in FIG. 11 in steps. FIG. 16 is a diagram showing a gate driver that outputs gate signals applied to the pixel circuit illustrated in FIG. 11. FIGS. 17 to 21 are drawings showing a display panel according to an embodiment of the present specification. FIG. 22 is a drawing showing a display device according to the first embodiment of the present specification. FIG. 23 is a waveform diagram showing signals applied to a display device according to the first embodiment of the present specification. FIGS. 24 to 31 are drawings showing the operation of a display device according to the first embodiment of the present specification in steps. FIG. 32 is a drawing showing a display device according to a second embodiment of the present specification. FIG. 33 is a waveform diagram showing signals applied to a display device according to a second embodiment of the present specification. The advantages and features of the invention disclosed in this specification, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the accompanying drawings. The invention is not limited to the embodiments disclosed below but may be implemented in various different forms; the embodiments are provided merely to ensure that the disclosure of the invention is complete and to fully inform those skilled in the art of the scope of the invention, and the invention is defined only by the scope of the claims. In describing the present invention, detailed descriptions of related prior art are omitted if it is determined that such descriptions may unnecessarily obscure the essence of the invention. Where terms such as "comprising," "may include," "having," "consisting of," etc. are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may be interpreted as plural unless specifically stated otherwise. When positional and interconnected relationships between two components are described, such as 'on', 'on top of', 'under', 'next to', 'connect or couple', or 'crossing or intersecting', one or more other components may be interposed between the components unless otherwise noted, such as 'immediately' or 'directly'. When temporal sequences are described using 'after', 'foll