KR-20260064073-A - DEVICE FOR PERFORMING DEVICE-TO-DEVICE COMMUNICATION BASED ON HIGH-SPEED SERIAL INTERFACE AND OPERATION METHOD THEREOF

Abstract

A first device communicating with a second device through a high-speed serial interface according to an exemplary embodiment of the present disclosure comprises an interface controller configured to restore data received through the high-speed serial interface and a component configured to perform a predetermined operation based on the restored data, wherein the interface controller comprises a restoration clock domain circuit configured to operate based on a restoration clock corresponding to the data transmission speed of the high-speed serial interface and a local clock domain circuit configured to operate based on a local clock having a frequency that is adaptively controlled according to the frequency of the restoration clock.

Inventors

• 국동현
• 유어진

Assignees

• 주식회사 파네시아

Dates

Publication Date

20260507

Application Date

20241031

Claims (20)

1. In a first device communicating with a second device via a high-speed serial interface, An interface controller configured to restore data received through the above high-speed serial interface; and It includes a component configured to perform a specific operation based on restored data, and The above interface controller is, A recovery clock domain circuit configured to operate based on a recovery clock corresponding to the data transmission speed of the high-speed serial interface; and A first device characterized by including a local clock domain circuit configured to operate based on a local clock having a frequency that is adaptively controlled according to the frequency of the above-mentioned restoration clock.
2. In paragraph 1, The above high-speed serial interface is, A first device characterized by being implemented as any one of a CXL (compute express link) interface, a PCIe (peripheral component interconnect express) interface, a SATA (serial AT attachment) interface, a USB (universal serial bus) interface, a DisplayPort interface, or an Ethernet interface.
3. In paragraph 1, The above restoration clock domain circuit is, A deserialization register configured to deserialize the received data based on the above restoration clock; and It includes an elastic buffer configured to store data deserialized from the deserialization register based on a divided recovery clock and output the stored data to the local clock domain circuit based on the local clock, and The frequency of the above local clock is, A first device characterized by having a frequency higher than that of the divided recovery clock.
4. In paragraph 3, The above elastic buffer is, A first device characterized by being composed of a single slot for storing deserialized data received at once from the above deserialization register.
5. In paragraph 3, The above local clock domain circuit is, A first device characterized by including a decoder configured to decode data output from the elastic buffer based on the local clock.
6. In paragraph 1, A first device characterized in that the above-mentioned restoration clock domain circuit and the above-mentioned local clock domain circuit correspond to the PHY layer.
7. In paragraph 1, The above interface controller is, A first device characterized by being further configured to determine the data transmission speed of the high-speed serial interface by signaling with the second device through the high-speed serial interface during an initial setup period, and to set the frequency of the local clock based on the determined data transmission speed.
8. In Paragraph 7, The above interface controller is, A first device characterized by being further configured to change the data transmission speed of the high-speed serial interface by signaling with the second device through the high-speed serial interface in the communication section, and to change the frequency of the local clock based on the changed data transmission speed.
9. In Paragraph 7, The above interface controller is, A first device characterized by being configured to detect a fluctuation in the frequency of the restoration clock in a communication section and to adjust the frequency of the local clock based on the detection result.
10. In Paragraph 7, The above interface controller is, A first device characterized by being configured to detect at least one parameter related to a fluctuation factor of the frequency of the restoration clock in a communication section, and to adjust the frequency of the local clock based on the detection result.
11. In Paragraph 10, The above at least one parameter is, A first device characterized by including at least one of a first parameter related to a transmission media delay of the high-speed serial interface, a second parameter related to crosstalk between lanes of the high-speed serial interface, a third parameter related to electromagnetic interference within the first device, a fourth parameter related to the temperature of the first device, and a fifth parameter related to the length between lanes of the high-speed serial interface.
12. In paragraph 1, The above component is, When the above-mentioned first device is implemented as a host device, it is implemented as a processor, and A first device characterized by being implemented as a memory device when the first device is implemented as a storage device.
13. In a first device communicating with a second device via a high-speed serial interface, An interface controller configured to restore data received through the above high-speed serial interface; and It includes a component configured to perform a specific operation based on restored data, and The above interface controller is, A deserialization register configured to deserialize the received data based on a recovery clock corresponding to the data transmission speed of the high-speed serial interface; An elastic buffer configured to store data deserialized from the deserialization register based on a divided recovery clock and output the stored data based on a local clock; A decoder configured to decode data output from the elastic buffer based on the local clock; and A first device characterized by including a control circuit configured to control the local clock such that the frequency of the local clock is higher than the frequency of the divided restored clock.
14. In Paragraph 13, The above interface controller is, A recovery clock PLL (phased locked loop) configured to generate the above recovery clock; and It further includes a local clock PLL configured to generate the above local clock, and The above control circuit is, A first device characterized by being further configured to control the frequency of the local clock by providing a control signal to the local clock PLL.
15. In Paragraph 13, The above-mentioned divided recovery clock is, A first device characterized by generating the above recovery clock by dividing it by a real number corresponding to the number of symbols deserialized at once from the above deserialization register.
16. In Paragraph 13, The above control circuit is, A first device characterized by being further configured to control the local clock such that the frequency of the local clock becomes an integer multiple of the frequency of the divided restored clock.
17. In Paragraph 13, The above control circuit is, A first device characterized by being further configured to control the local clock such that the frequency of the local clock exceeds 1 times the frequency of the divided recovery clock and is less than 2 times the frequency of the divided recovery clock.
18. In Paragraph 13, The above control circuit is, A first device characterized by being further configured to detect a fluctuation in the frequency of the restoration clock, determine based on the detection result that the frequency of the divided restoration clock is higher than the frequency of the local clock, and adjust the frequency of the local clock to be higher based on the determination result.
19. In Paragraph 18, The above control circuit is, A first device characterized by being further configured to detect fluctuations in the frequency of the restoration clock based on the storage state of the elastic buffer.
20. In Paragraph 13, The above control circuit is, A first device characterized by detecting at least one parameter related to a variation factor of the frequency of the restoration clock, predicting that the frequency of the divided restoration clock is higher than the frequency of the local clock based on the detection result, and further configured to adjust the frequency of the local clock to be higher based on the prediction result.

Description

Device for performing device-to-device communication based on a high-speed serial interface and method of operation thereof The technical concept of the present disclosure is to a device that performs communication between devices based on a high-speed serial interface. Recently, technologies regarding high-speed serial interfaces have been proposed for high-speed data communication between devices. Among these technologies, PCIe (Peripheral Component Interconnect Express) and CXL (Compute Express Link) related technologies are being actively researched. A device for performing communication using a high-speed serial interface may include a recovered clock domain circuit that performs operations based on a recovered clock according to communication between devices, and a local clock domain circuit that performs operations based on a local clock within the device. The recovered clock domain circuit may include an elastic buffer used to align symbols received by lane to the local clock. Specifically, symbols are input into the elastic buffer based on a divided recovered clock, and symbols stored based on the local clock can be output based on the local clock. The elastic buffer can be operated by adding a specific symbol to the elastic buffer when the frequency of the local clock is faster than the frequency of the divided recovery clock, or by deleting a specific symbol stored in the elastic buffer when the frequency of the local clock is slower than the frequency of the divided recovery clock. However, the operation method of the elastic buffer described above results in high latency, which can place a burden on high-speed data communication; therefore, improvements are necessary. FIG. 1 is a block diagram showing the schematic configuration of an electronic system according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram showing an interface controller according to an exemplary embodiment of the present disclosure. FIG. 3A is a block diagram showing an interface controller according to an exemplary embodiment of the present disclosure, and FIG. 3B is a diagram for explaining the operation of the elastic buffer of FIG. 3A. FIG. 4 is a drawing for illustrating one embodiment of an elastic buffer according to an exemplary embodiment of the present disclosure. FIG. 5 is a flowchart for explaining the operation method of a first device and a second device according to an exemplary embodiment of the present disclosure. FIG. 6 is a flowchart for explaining the operation method of a first device and a second device according to an exemplary embodiment of the present disclosure. FIG. 7 is a flowchart for explaining the method of operation of a device according to an exemplary embodiment of the present disclosure. FIGS. 8A and FIGS. 8B are drawings for illustrating a control circuit implemented to perform the operation according to FIG. 7. FIG. 9 is a flowchart for explaining the method of operation of a device according to an exemplary embodiment of the present disclosure. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. The embodiments of the present disclosure are provided to more fully explain the present disclosure to those skilled in the art. Since the present disclosure is subject to various modifications and may take various forms, specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the present disclosure to specific forms, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the present disclosure. Similar reference numerals are used for similar components in describing each drawing. In the attached drawings, the dimensions of structures are depicted enlarged or reduced compared to the actual dimensions for the sake of clarity of the present disclosure. The terms used in this application are used merely to describe specific embodiments and are not intended to limit the disclosure. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as “comprising” or “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Additionally, terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. Such terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of th