KR-20260064099-A - Semiconductor memory device

Abstract

The present invention provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including an active region defined by a device isolation film, a bit line structure disposed on the substrate including a cell conduction line and a cell line capping film, wherein the cell line capping film includes a bit line structure extending along the upper surface of the cell conduction line, storage contacts disposed on both sides of the bit line structure and connected to the active region, storage pads disposed on the storage contacts and connected to the storage contacts, and a data storage pattern disposed on the upper surface of the cell line capping film and connected to the storage pads, wherein the storage pads include an upper storage pad and a lower storage pad disposed between the upper storage pad and the storage contacts, and on the upper surface of the cell line capping film, the width of the upper storage pad increases as it moves away from the upper surface of the cell line capping film.

Inventors

• 박준희
• 권호준
• 김남건

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241031

Claims (10)

1. A substrate including an active region defined by a device isolation layer; A bit line structure disposed on the above substrate and comprising a cell conductive line and a cell line capping film, wherein the cell line capping film is a bit line structure extending along the upper surface of the cell conductive line; Storage contacts disposed on both sides of the bit line structure and connected to the active area; A storage pad disposed on the storage contact and connected to the storage contact; and It includes a data storage pattern disposed on the upper surface of the cell line capping film and connected to the storage pad, and The above storage pad includes an upper storage pad and a lower storage pad disposed between the upper storage pad and the storage contact, and A semiconductor memory device in which, on the upper surface of the cell line capping film, the width of the upper storage pad increases as it moves away from the upper surface of the cell line capping film.
2. In Article 1, The upper storage pad above includes a first part and a second part, and The first portion of the upper storage pad is positioned on the upper surface of the cell line capping film, and A semiconductor memory device in which the second portion of the upper storage pad is disposed between the first portion of the upper storage pad and the lower storage pad.
3. In Article 1, The entire upper storage pad is a semiconductor memory device disposed on the upper surface of the cell line capping film.
4. In Article 1, The above storage contact includes a semiconductor material, and The above upper storage pad and the above lower storage pad are each semiconductor memory devices comprising a metal or a compound containing a metal.
5. In Article 1, It further includes a pad separation pattern covering the side wall of the upper storage pad, and The above upper storage pad includes an upper pad filling film and an upper pad silicide film, and The above upper pad silicide film is a semiconductor memory device disposed along the interface between the upper pad filling film and the pad separation pattern.
6. In Article 5, The upper storage pad above is in contact with the lower storage pad, and A semiconductor memory device in which the upper pad silicide film does not extend along the interface between the upper pad filling film and the lower storage pad.
7. A substrate including an active region defined by a device isolation layer; A bit line structure disposed on the above substrate and comprising a cell conductive line and a cell line capping film stacked in a first direction, wherein the cell line capping film is a bit line structure extending along the upper surface of the cell conductive line; Storage contacts disposed on both sides of the bit line structure and connected to the active area; A storage pad disposed on the storage contact and connected to the storage contact; and It includes a data storage pattern disposed on the upper surface of the cell line capping film and connected to the storage pad, and The above storage pad includes an upper storage pad and a lower storage pad disposed between the upper storage pad and the storage contact, and The upper storage pad includes an upper surface connected to the data storage pattern, a bottom surface in contact with the lower storage pad and the bit line structure, and a side wall connecting the upper surface of the upper storage pad and the bottom surface of the upper storage pad. The above upper storage pad includes an upper pad filling film and an upper pad silicide film, and The above upper pad silicide film is a semiconductor memory device comprising a sidewall of the above upper storage pad.
8. In Article 7, A semiconductor memory device in which the upper pad silicide film does not extend along the interface between the upper pad filling film and the lower storage pad.
9. A substrate comprising a cell region and a periregion defined around the cell region, wherein the cell region comprises a cell active region defined by a cell device isolation layer; A bit line structure disposed on the cell region of the substrate and comprising a cell conductive line and a cell line capping film, wherein the cell line capping film is a bit line structure extending along the upper surface of the cell conductive line; A perigate structure disposed on the peri region of the substrate and comprising a perigate conductive film; ferry wiring lines arranged on the above ferry gate structure; Storage contacts connected to the cell active area above; Storage pads connected to the above storage contact; A pad separation pattern for separating adjacent storage pads; and It includes data storage patterns disposed on the upper surface of the cell line capping film and connected to the storage pad, and Each of the above storage pads includes an upper storage pad and a lower storage pad disposed between the upper storage pad and the storage contact, and The upper storage pad comprises a first portion disposed on the upper surface of the cell line capping film and a second portion disposed between the first portion of the upper storage pad and the lower storage pad. A semiconductor memory device in which, in the first portion of the upper storage pad, the width of the upper storage pad increases as it moves away from the upper surface of the cell line capping film.
10. In Article 9, The above upper storage pad includes an upper pad filling film and an upper pad silicide film, and The above upper pad silicide film is a semiconductor memory device disposed along the interface between the upper pad filling film and the pad separation pattern.

Description

Semiconductor memory device The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having a plurality of mutually intersecting wiring lines and buried contacts. As semiconductor devices become increasingly highly integrated, individual circuit patterns are becoming finer in order to implement more semiconductor devices in the same area. In other words, as the integration density of semiconductor devices increases, the design rules for the components of semiconductor devices are decreasing. In highly scaled semiconductor devices, the process of forming multiple wiring lines and multiple buried contacts (BCs) interposed between them is becoming increasingly complex and difficult. FIG. 1 is a schematic layout diagram of a semiconductor memory device according to some embodiments. Figure 2 is a layout of the R region, which is part of the cell region of Figure 1. Figure 3 is a layout showing only the word lines and active area of Figure 2. Figure 4 is a cross-sectional view taken along A-A of Figure 1. Figures 5 and 6 are cross-sectional views taken along B-B and C-C of Figure 2, respectively. Figure 7 is an enlarged view of section P of Figure 4. Figure 8 is an enlarged view of section Q of Figure 5. FIGS. 9 and FIGS. 10 are drawings for illustrating a semiconductor memory device according to some embodiments. FIGS. 11 and FIGS. 12 are drawings for illustrating a semiconductor memory device according to some embodiments. FIGS. 13 to 15 are drawings for explaining a semiconductor memory device according to some embodiments. FIGS. 16 and 17 are drawings for illustrating a semiconductor memory device according to some embodiments. FIGS. 18 to 20 are drawings for illustrating a semiconductor memory device according to some embodiments. FIGS. 21 and FIGS. 22 are drawings for illustrating a semiconductor memory device according to some embodiments. FIGS. 23 and 24 are drawings for illustrating a semiconductor memory device according to some embodiments. FIG. 25 is a drawing for illustrating a semiconductor memory device according to some embodiments. FIGS. 26 to 31 are intermediate drawings for explaining a method for manufacturing a semiconductor memory device according to some embodiments. FIGS. 32 to 36 are intermediate drawings for explaining a method for manufacturing a semiconductor memory device according to some embodiments. In this specification, although terms such as "first," "second," etc. are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention. FIG. 1 is a schematic layout diagram of a semiconductor memory device according to some embodiments. FIG. 2 is a layout of the R region, which is part of the cell region of FIG. 1. FIG. 3 is a layout showing only the word line and active region of FIG. 2. FIG. 4 is a cross-sectional view taken along A-A of FIG. 1. FIG. 5 and FIG. 6 are cross-sectional views taken along B-B and C-C of FIG. 2, respectively. FIG. 7 is an enlarged view of the P portion of FIG. 4. FIG. 8 is an enlarged view of the Q portion of FIG. 5. For reference, FIG. 4 may be an exemplary cross-sectional view of a transistor forming region in the peri region. In FIG. 1, the cutting line A-A is shown as cutting along the first direction (DR1), but is not limited thereto. Unlike what is shown, the cutting line A-A may be shown as cutting along the second direction (DR2). In the drawings relating to a semiconductor memory device according to some embodiments, a Dynamic Random Access Memory (DRAM) is illustrated as an example, but is not limited thereto. Referring to FIGS. 1 to 3, a semiconductor memory device according to some embodiments may include a cell region (20), a cell region separator (22), and a ferri region (24). A cell region separator (22) may be formed along the perimeter of a cell region (20). The cell region separator (22) may separate the cell region (20) and the periphery region (24). The periphery region (24) may be defined around the cell region (20). The cell region (20) may include a plurality of cell active regions (ACTs). The cell active regions (ACTs) may be defined by a cell device isolation film (105 in FIG. 5) formed within a substrate (100 in FIG. 5). Due to the reduction of design rules for semiconductor memory devices, the cell active regions (ACTs) may be arranged in the form of a bar of a diagonal line or oblique line as illustrated. For example, the cell active regions (ACTs) may extend in a third direction (DR3). A plurality of gate electrodes may be arranged in a first direction (DR1) across the cell active region (ACT). The plurality of gate electrodes may extend parallel t