KR-20260064188-A - SEMICONDUCTOR DEVICE

Abstract

The present invention relates to a semiconductor device, and more specifically, comprises: a substrate including a logic cell region and an ESD cell region; a plurality of active pins provided on the ESD cell region and arranged in an alternating manner in a first direction, wherein the plurality of active pins include a first active pin and a second active pin arranged in an alternating manner spaced apart in the first direction; a device isolation layer defining the first active pin and the second active pin; a pair of source/drain patterns on each of the plurality of active pins, wherein the pair of source/drain patterns are spaced apart from each other in a second direction intersecting the first direction; a channel pattern between the pair of source/drain patterns; and a gate electrode extending in the first direction on the channel pattern, wherein each of the first and second active pins extends in the second direction, and the length of the first active pin in the second direction may be greater than the length of the second active pin in the second direction.

Inventors

• 유재현
• 박용희
• 박소라
• 신동관

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241031

Claims (10)

1. A substrate including a logic cell region and an ESD cell region; A plurality of active pins provided on the ESD cell region and arranged intersectingly in a first direction, wherein the plurality of active pins include first active pins and second active pins arranged intersectingly and spaced apart in the first direction; A device isolation layer defining the first active pins and the second active pins; A pair of source/drain patterns on each of the plurality of active pins, wherein the pair of source/drain patterns are spaced apart from each other in a second direction intersecting the first direction; Channel pattern between the above pair of source/drain patterns; and A gate electrode extending in the first direction on the channel pattern, comprising: Each of the first and second active pins extends in the second direction, and A semiconductor device in which the length of the first active pin in the second direction is greater than the length of the second active pin in the second direction.
2. In paragraph 1, A semiconductor device in which the length of the first active pin in the second direction is 1.5 to 3.5 times the length of the second active pin in the second direction.
3. In paragraph 1, A semiconductor device having a first N+ emitter region, a P+ base region, an N collector region, a P+ base region, and the first N+ emitter region sequentially arranged in the second direction on each of the first active pins.
4. In paragraph 1, A semiconductor device having a first N+ emitter region, a P+ base region, an N collector region, a P+ base region, and a second N+ emitter region sequentially arranged in the second direction on each of the second active pins.
5. In paragraph 1, A semiconductor device further comprising each of the above-mentioned second active pins and a third active pin spaced apart at a predetermined interval along the second direction.
6. In paragraph 5, A first N+ emitter region, a P+ base region, an N collector region, a P+ base region, and a second N+ emitter region are sequentially arranged in the second direction on each of the second active pins, and A semiconductor device having a second N+ emitter region, a P+ base region, an N collector region, a P+ base region, and a first N+ emitter region sequentially arranged in the second direction on the third active pin.
7. In paragraph 6, The width of the second N+ emitter region in the second direction on each of the second active pins is smaller than the width of the first N+ emitter region in the second direction, and A semiconductor device in which the width of the second N+ emitter region on the third active pin in the second direction is smaller than the width of the first N+ emitter region in the second direction.
8. In paragraph 3, A semiconductor device comprising an NPN bipolar transistor on each of the first active pins.
9. In paragraph 1, The distance between one of the first active pins and one of the second active pins is a first width, and A semiconductor device in which the distance between adjacent first active pins among the first active pins is a second width.
10. In Paragraph 9, The above second width is a semiconductor device larger than the above first width.

Description

Semiconductor Device The present invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising an ESD device (Electro-Static Discharge device or Electro-Static Discharge cell) having a fin pattern. Due to characteristics such as miniaturization, multifunctionality, and/or low manufacturing costs, semiconductor devices are receiving significant attention as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements. Recently, with the increasing speed and low power consumption of electronic devices, embedded semiconductor devices are also required to have fast operating speeds and/or low operating voltages. To meet these requirements, more highly integrated semiconductor devices are necessary. However, as the integration of semiconductor devices intensifies, their electrical characteristics and production yield may decrease. Accordingly, much research is being conducted to improve the electrical characteristics and production yield of semiconductor devices. Relatively high voltages can be generated in the vicinity of an integrated circuit due to the buildup of electrostatic charges in semiconductor devices. These high voltages can be caused by the input or output buffers of the integrated circuit, or by a person touching package pins electrically connected to the input or output buffers. When electrostatic charges are discharged, relatively high currents can be generated at the input and output nodes of the integrated circuit. Such electrostatic discharge (ESD) can destroy or damage the entire integrated circuit. Accordingly, much research is being conducted to electrically ground the currents caused by electrostatic discharge in semiconductor devices. FIG. 1 is a schematic circuit diagram showing an electrostatic discharge (ESD) protection circuit including a logic cell and an ESD cell. FIG. 2 is a plan view for illustrating a semiconductor device including an ESD cell according to embodiments of the present invention. FIGS. 3a to 3d are cross-sectional views along the lines A-A', B-B', C-C', and D-D' of FIG. 2, respectively. FIGS. 3e to 3h are cross-sectional views along the lines A-A', B-B', C-C', and D-D' of FIG. 2, respectively, and cross-sectional views according to other embodiments of FIGS. 3a to 3d. FIG. 4 is a plan view for illustrating a semiconductor device including an ESD cell according to another embodiment of the present invention. Figure 5 is a cross-sectional view along the line D-D' of Figure 4. FIG. 6 is a plan view for illustrating a semiconductor device including an ESD cell according to another embodiment of the present invention. Figure 7 is a cross-sectional view along the line D-D' of Figure 6. FIG. 8 is a plan view for illustrating a semiconductor device including an ESD cell according to another embodiment of the present invention. FIG. 9 is a plan view for illustrating a semiconductor device including an ESD cell according to another embodiment of the present invention. FIGS. 10a to 10d are cross-sectional views along the lines A-A', B-B', C-C', and D-D' of FIG. 9, respectively. Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 is a schematic circuit diagram showing an electrostatic discharge (ESD) protection circuit including a logic cell and an ESD cell. Referring to FIG. 1, the semiconductor device may include an ESD cell (10) and a logic cell (20). The ESD cell (10) may be a FinFET (Fin Field-Effect Transistor; FinFET) used as an ESD power clamp. The logic cell (20) may form a trigger circuit for the ESD cell (10), and the trigger circuit may be an ESD detection circuit. The drain region (12) and source region (16) of the ESD cell (10) may be connected to a power supply node (VDD) and a voltage node (VSS), respectively. Specifically, the drain region (12) may be connected to the power supply node (VDD), and the source region (16) may be connected to the voltage node (VSS). The voltage node (VSS) may be an electrical ground. The input of the logic cell (20) can be connected to the connection node (Vin), and the output of the logic cell (20) can be connected to the gate (14) of the ESD cell (10). If an ESD transient occurs on the power supply node (VDD), the voltage on the connection node (Vin) can be lowered, for example, to 0V. Since the logic cell (20) is an inverter, the gate voltage of the gate (14) of the ESD cell (10) can be a high enough voltage to turn on the ESD cell (10). Accordingly, the ESD current can flow through the ESD cell (10). If no ESD transient occurs on the power supply node (VDD), the voltage on the connection node (Vin) can be equal to the vo