KR-20260064213-A - Three dimensional semiconductor device and method for manufacturing the same

Abstract

A three-dimensional semiconductor device according to the present invention comprises: a bit line spaced apart from a substrate and extending along a direction perpendicular to the lower surface of the substrate; first semiconductor patterns provided on one side of the bit line, wherein the first semiconductor patterns include a first top-most pattern; and a word line surrounding the first and second semiconductor patterns, wherein the first top-most pattern includes a first top edge portion and a second top edge portion spaced apart from each other in a first direction, and a first top channel region between the first top edge portion and the second top edge portion, wherein the thickness of the first top edge portion is greater than the thickness of the first top channel region and the thickness of the second top edge portion is greater than the thickness of the first top channel region.

Inventors

• 한진우
• 한상일
• 오규환
• 한승욱

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241031

Claims (10)

1. A bit line spaced apart from the substrate and extending along a direction perpendicular to the lower surface of the substrate; It includes first semiconductor patterns provided on one side of the bit line, and the first semiconductor patterns include a first top-most pattern; and It includes a word line surrounding the first semiconductor patterns, The first top-most pattern includes a first top edge portion and a second top edge portion spaced apart from each other in a first direction, and a first top channel region between the first top edge portion and the second top edge portion. The thickness of the first top edge portion is greater than the thickness of the first top channel region, and A three-dimensional semiconductor device in which the thickness of the second top edge portion is greater than the thickness of the first top channel region.
2. In Article 1, The width of the first top edge portion in the second direction is greater than the width of the first top channel area in the second direction, and The second direction is parallel to the lower surface of the substrate and orthogonal to the first direction, and A three-dimensional semiconductor device in which the width of the second direction of the second top edge portion is greater than the width of the second direction of the first top channel region.
3. In Article 1, The upper and lower surfaces of each of the first top edge portion and the second top edge portion are doped three-dimensional semiconductor devices.
4. In Article 1, A three-dimensional semiconductor device in which the upper and lower surfaces of each of the first top edge portion and the second top edge portion contain N-type impurities.
5. In Article 1, Each of the first top edge portion and the second top edge portion includes an upper surface, a lower surface, and a central portion between the upper surface and the lower surface, and A three-dimensional semiconductor device in which the doping concentration of each of the first top edge portion and the second top edge portion has a maximum value on the upper surface, decreases as it moves from the upper surface toward the center, and then increases again as it moves from the center toward the lower surface.
6. In Article 1, A three-dimensional semiconductor device in which the upper and lower portions of each of the first top edge portion and the second top edge portion are formed by a selective epitaxy growth (SEG) process.
7. In Article 1, The above-mentioned first top edge portion includes a first side, and The above-mentioned second top edge portion includes a second side, and The first side and the second side face each other in the first direction, and The above bit line is provided on the first side of the first top edge portion, and A three-dimensional semiconductor device further comprising a data storage pattern on the second side of the second top edge portion.
8. In Article 7, The above data storage pattern is a three-dimensional semiconductor device comprising a storage electrode, a plate electrode, and a capacitor dielectric film interposed between them.
9. In Article 1, It includes second semiconductor patterns provided on the other side of the bit line, and the second semiconductor patterns further include a second highest level pattern. The above second top pattern includes a third top edge portion, a fourth top edge portion, and a second top channel region between the third top edge portion and the third top edge portion, and The thickness of the third top edge portion is greater than the thickness of the second top channel region, and A three-dimensional semiconductor device in which the thickness of the fourth top edge portion is greater than the thickness of the second top channel region.
10. In Article 9, The above-mentioned third top edge portion includes a third side, and The above-mentioned fourth top edge portion includes a fourth side, and The third side and the fourth side face each other in the first direction, and The above bit line is provided on the third side of the third top edge portion, and A three-dimensional semiconductor device further comprising a data storage pattern on the fourth side of the fourth top edge portion.

Description

Three-dimensional semiconductor device and method for manufacturing the same The present invention relates to a three-dimensional semiconductor device and a method for manufacturing the same, and more specifically, to a three-dimensional semiconductor device with improved reliability and integration density. Due to characteristics such as miniaturization, multifunctionality, and/or low manufacturing costs, semiconductor devices are receiving significant attention as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements. Recently, with the increasing speed and low power consumption of electronic devices, embedded semiconductor devices are also required to have fast operating speeds and/or low operating voltages. To meet these requirements, more highly integrated semiconductor devices are necessary. However, as the integration of semiconductor devices intensifies, their electrical characteristics and production yield may decrease. Accordingly, much research is being conducted to improve the electrical characteristics and production yield of semiconductor devices. FIG. 1 is a schematic circuit diagram showing a three-dimensional semiconductor device according to some embodiments of the present invention. FIGS. 2a, FIGS. 2b and FIGS. 2c are schematic perspective views of a three-dimensional semiconductor device according to some embodiments of the present invention. FIG. 3a is a perspective view showing semiconductor patterns, word lines, bit lines, and data storage patterns of a three-dimensional semiconductor device according to some embodiments of the present invention. FIG. 3b is a perspective view showing semiconductor patterns, word lines, bit lines, data storage patterns, precharge lines, and global bit lines of a three-dimensional semiconductor device according to some embodiments of the present invention. FIG. 4 is a plan view of a three-dimensional semiconductor device according to some embodiments of the present invention. FIG. 5a is a cross-sectional view corresponding to line AA' in FIG. 4. FIG. 5b is a cross-sectional view corresponding to line BB' of FIG. 4. Figure 6a is an enlarged view corresponding to the M region of Figure 5a. Figure 6b is an enlarged view corresponding to the N region of Figure 5a. Figures 7a, 7b, and 7c are graphs showing the doping concentration according to the X-ray of Figure 6a. FIG. 7d is a diagram illustrating a plurality of MUX transistors of a three-dimensional semiconductor device to explain an embodiment of the present invention. FIGS. 8a and 8b are enlarged views corresponding to the M area of FIG. 5a, intended to illustrate other embodiments of the present invention. FIG. 8c is a cross-sectional view corresponding to line AA' in FIG. 4, intended to illustrate other embodiments of the present invention. FIGS. 9 to 18 are drawings illustrating a method for manufacturing a three-dimensional semiconductor device according to some embodiments of the present invention. Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 is a schematic circuit diagram showing a three-dimensional semiconductor device according to some embodiments of the present invention. Referring to FIG. 1, a three-dimensional semiconductor device may include a memory cell array (1), a row decoder (2), a sense amplifier (3), a column decoder (4), and control logic (5). A memory cell array (1) may include word lines (WL), bit lines (BL), source lines (SL), and memory cells (MC). The memory cells (MC) may be arranged in three dimensions, and the memory cells (MC) may be connected to one word line (WL), one bit line (BL), and one source line (SL). In some embodiments, each of the memory cells (MC) may be composed of a single transistor comprising a memory film (or data storage film). The row decoder (2) can decode an externally input address and select one of the word lines (WL) of the memory cell array (1). The address decoded by the row decoder (2) can be provided to a row driver (not shown), and the row driver can provide a predetermined voltage to the selected word line (WL) and the unselected word lines (WL), respectively, in response to the control of the control circuits. The sense amplifier (3) can detect and amplify the voltage difference between the selected bit line (BL) and the reference bit line according to the address decoded from the column decoder (4) and output it. The column decoder (4) can provide a data transmission path between the sense amplifier (3) and an external device (e.g., a memory controller). The column decoder (4) can decode an externally input address and select any one of the bit lines (BL). The co