KR-20260064222-A - Method for OPC and method for manufacturing semiconductor device using the same

KR20260064222AKR 20260064222 AKR20260064222 AKR 20260064222AKR-20260064222-A

Abstract

A method for manufacturing a semiconductor device according to the present invention comprises: performing optical proximity correction on a layout; and forming a photoresist pattern on a substrate using a photomask fabricated with the corrected layout, wherein the optical proximity correction comprises: generating a contour for a target pattern of the layout; generating first to fourth error vectors between first to fourth edge segments of the target pattern and the contour; and sequentially performing a first correction step and a second correction step for the target pattern to generate a correction pattern, wherein the first correction step comprises moving the first edge segment based on the first error vector and moving the second edge segment based on the second error vector, and the second correction step comprises moving the third and fourth edge segments based on the sum of the third error vector and the fourth error vector, and wherein the first and second edge segments face each other and the third and fourth edge segments face each other.

Inventors

김선엽
손완기
장준영

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20241031

Claims (10)

Performing optical proximity correction on the layout; and The method includes forming a photoresist pattern on a substrate using a photomask produced with the corrected layout above, wherein The above optical proximity correction is: Generating a contour for the target pattern of the above layout; Generating first to fourth error vectors between the first to fourth edge segments of the target pattern and the contour; and The method includes generating a correction pattern by sequentially performing a first correction step and a second correction step for the above target pattern, wherein The first correction step includes moving the first edge segment based on the first error vector and moving the second edge segment based on the second error vector, The second correction step comprises moving the third and fourth edge segments based on the sum of the third error vector and the fourth error vector, and The first and second edge segments above face each other, A method for manufacturing a semiconductor device in which the above-mentioned third and fourth edge segments face each other.
In Article 1, It further includes setting the first length ratio of the above correction pattern, A method for manufacturing a semiconductor device, wherein the second correction step further comprises additionally moving the third and fourth edge segments to match the first length-short ratio of the correction pattern.
In Article 1, The above contour is the first contour, and The above correction pattern is a first correction pattern, and A method for manufacturing a semiconductor device, further comprising generating a second contour for the first correction pattern.
In Paragraph 3, After generating the second contour, generating 5 to 8 error vectors between the target pattern and the second contour; and A method for manufacturing a semiconductor device further comprising sequentially performing a third correction step and a fourth correction step for the target pattern based on the 5th to 8th error vectors to generate a second correction pattern.
In Paragraph 4, A method for manufacturing a semiconductor device in which the length-to-length ratio of the first correction pattern is substantially the same as the length-to-length ratio of the second correction pattern.
In Article 1, The above target pattern includes multiple target patterns within the layout, and A method for manufacturing a semiconductor device in which the above target patterns are arranged in a zigzag shape along one direction.
Performing optical proximity correction on the layout; and The method includes forming a photoresist pattern on a substrate using a photomask produced with the corrected layout above, wherein The above optical proximity correction is: Generating a contour for the target pattern of the above layout; Generating a first 4th error vector between the first to fourth edge segments of the target pattern and the contour; Generating a correction pattern by sequentially performing a first correction step for each of the first and second edge segments facing each other and a second correction step for each of the third and fourth edge segments facing each other; and Includes setting the first length ratio of the above correction pattern, The above second correction step is: Moving the third and fourth edge segments based on the sum of the third error vector and the fourth error vector; and A method for manufacturing a semiconductor device comprising additionally moving each of the third and fourth edge segments to match the first length-short ratio of the correction pattern.
In Article 7, The above contour is the first contour, and The above correction pattern is a first correction pattern, and Further comprising generating a second contour for the first correction pattern, A method for manufacturing a semiconductor device in which the aspect ratio of the first contour is substantially the same as the aspect ratio of the second contour.
In Paragraph 8, After generating the second contour, generating 5 to 8 error vectors between the target pattern and the second contour; and The method further includes generating a second correction pattern by sequentially performing a third correction step and a fourth correction step for the target pattern based on the fifth to eighth error vectors, wherein A method for manufacturing a semiconductor device in which the length-to-length ratio of the second correction pattern is substantially the same as the first length-to-length ratio of the first correction pattern.
Generating contours for the target pattern of the layout; Generating first to fourth error vectors between the first to fourth edge segments of the target pattern and the contour; Generating a correction pattern by sequentially performing a first correction step and a second correction step for the above target pattern; Producing a photomask with the corrected layout including the above correction pattern; Forming an etching target layer and a photoresist layer on a substrate; Forming photoresist patterns by exposing and developing the photoresist layer with the photomask; and Patterning the etching target layer using the above photoresist patterns, wherein The first correction step comprises moving the first edge segment based on the first error vector and moving the second edge segment facing the first edge segment based on the second error vector, A method for manufacturing a semiconductor device, wherein the second correction step comprises moving the third and fourth edge segments facing each other based on the sum of the third error vector and the fourth error vector.

Description

OPC method and method for manufacturing semiconductor device using the same The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device using an OPC method. Due to characteristics such as miniaturization, multifunctionality, and/or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements. As the electronics industry advances, demands regarding the characteristics of semiconductor devices are steadily increasing. For example, there is a growing demand for high reliability, high speed, and/or multifunctionality. To meet these requirements, the internal structures of semiconductor devices are becoming increasingly complex, and semiconductor devices are becoming more highly integrated. FIG. 1 is a block diagram showing a computer system for performing semiconductor design according to embodiments of the present invention. FIG. 2 is a flowchart showing a method for designing and manufacturing a semiconductor device according to embodiments of the present invention. 3 is a conceptual diagram showing a photolithography system using a photomask fabricated according to embodiments of the present invention. FIGS. 4a, FIGS. 4b, and FIGS. 4c are flowcharts schematically illustrating specific processes of optical proximity correction according to embodiments of the present invention. FIGS. 5 to 11 are layout plans for explaining optical proximity correction. FIG. 12 is a plan view showing a photomask according to embodiments of the present invention. FIG. 13 is a conceptual diagram showing the formation of photoresist patterns on a substrate using the photomask of FIG. 12. FIGS. 14 to 21 are drawings illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a computer system for performing semiconductor design according to embodiments of the present invention. Referring to FIG. 1, the computer system may include a CPU (10), a working memory (30), an input/output device (50), and an auxiliary storage device (70). The computer system may be provided as a dedicated device for the layout design of the present invention. The computer system may be equipped with various design and verification simulation programs. The CPU (10) can execute software (applications, operating systems, device drivers) to be executed in a computer system. The CPU (10) can execute an operating system (OS, not shown) loaded into working memory (30). The CPU (10) can execute various applications to be run on the operating system (OS). For example, the CPU (10) can execute a layout design tool (32) and/or an OPC tool (34) loaded into working memory (30). An operating system (OS) or applications may be loaded into the working memory (30). When booting the computer system, an OS image (not shown) stored in the auxiliary storage device (70) may be loaded into the working memory (30) according to the boot sequence. Various input/output operations of the computer system may be supported by the operating system (OS). Applications may be loaded into the working memory (30) for selection by the user or for providing basic services. A layout design tool (32) and/or an OPC tool (34) may be loaded from the auxiliary storage device (70) into the working memory (30). The layout design tool (32) may be equipped with a bias function that can change the shape and position of specific layout patterns differently from what is defined by design rules. The layout design tool (32) may perform a Design Rule Check (DRC) under the changed bias data conditions. The OPC tool (34) may perform Optical Proximity Correction (OPC) on the layout data output from the layout design tool (32). The working memory (30) may be a volatile memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory), or a non-volatile memory such as PRAM, MRAM, ReRAM, FRAM, or NOR flash memory. The input/output device (50) controls user input and output from user interface devices. For example, the input/output device (50) may be equipped with a keyboard or a monitor to receive information from the designer. Using the input/output device (50), the designer may receive information regarding semiconductor regions or data paths that require adjusted operating characteristics. Through the input/output device (50), the processing process and processing results of the OPC tool (34) may be displayed. An auxiliar