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KR-20260064239-A - SEMICONDUCTOR DEVICE INCLUDING ACTIVE PORTION AND BIT LINE

KR20260064239AKR 20260064239 AKR20260064239 AKR 20260064239AKR-20260064239-A

Abstract

A semiconductor device comprising an active portion and a bit line is provided. The semiconductor device comprises a first active portion; a device isolation region on the side of the first active portion; and a bit line connected to the first active portion. The first active portion comprises a first region in contact with the device isolation region and a second region extending upward from the first region and spaced apart from the device isolation region. The bit line comprises a line portion extending in a first horizontal direction; and a contact portion disposed below the line portion and connected to the second region of the first active portion.

Inventors

  • 한은수
  • 박찬훈
  • 전하영

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20241031

Claims (10)

  1. First active part; A device isolation region on the side of the first active portion; and It includes a bit line connected to the first active part, The first active portion includes a first region in contact with the device isolation region and a second region extending upward from the first region and spaced apart from the device isolation region. The above bitline is, A line portion extending in the first horizontal direction; and A semiconductor device comprising a contact portion disposed below the above-mentioned line portion and connected to the second region of the above-mentioned first active portion.
  2. In Article 1, Insulating spacer structures including contact spacers and line spacers are further included, The above contact spacer is disposed on the side of the second region of the first active portion and on the side of the contact portion, and The above line spacer is positioned on the side of the above line portion, and The above-mentioned device isolation region is in contact with the side of the first region of the above-mentioned first active portion, and The above contact spacer is a semiconductor device that contacts the side of the second region of the first active portion and the side of the contact portion.
  3. In Article 1, The above line portion includes a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence, and The above contact portion extends from the first conductive layer of the above line portion, and The above first conductive layer is a semiconductor device comprising doft polysilicon.
  4. In Article 1, Insulating spacer structure including contact spacers and line spacers; and It further includes a second active portion adjacent to the first active portion and spaced apart from the first active portion by the device isolation region, The above contact spacer is disposed on the side of the second region of the first active portion and on the side of the contact portion, and The above line spacer is positioned on the side of the above line portion, and The upper surface of the second active part is positioned at a first height level, and The upper surface of the second region of the first active part is positioned at a second height level, and The area between the side of the first region of the first active part and the side of the second region of the first active part is positioned at a third height level, and The second height level is positioned at a lower level than the first height level, and A semiconductor device in which, in the first active portion, the vertical thickness of the second region is greater than the width of the second region.
  5. First active portion and second active portion adjacent to each other; A device isolation region between the first active portion and the second active portion; A bit line electrically connected to the first active part above; A contact structure electrically connected to the second active part; and It includes an information storage structure electrically connected to the above contact structure, The above first active portion has an upper surface that is convex toward the top, and The above bit line is a semiconductor device comprising a contact portion that contacts the upper surface of the first active portion and a line portion disposed on the contact portion and extending in a first horizontal direction.
  6. In Article 5, In addition to insulating spacers, The first active portion comprises a first region in contact with the device isolation region and a second region spaced apart from the device isolation region and in contact with the insulating spacer. The insulating spacer includes a contact spacer on the side of the second region of the first active part and the side of the contact part, and a line spacer on the side of the line part. The upper surface of the second active part is positioned at a higher level than the upper surface of the first active part, and The above-mentioned device isolation region is a semiconductor device extending between the above-mentioned contact spacer and the above-mentioned second active portion.
  7. Active regions; Device isolation region between the above active regions; Gate structures extending into the device isolation region across the active regions; and It includes bit lines connected to the above active regions, Each of the above active regions includes a first active portion and a second active portion separated from each other by a gate structure that crosses the active region among the gate structures, and The above active regions include a first active region, and The above bit lines include a first bit line connected to the first active portion of the first active region, and The first active portion of the first active region is, A first region having a side in contact with the above-mentioned device isolation region; and It includes a second region that extends upward from the first region and is spaced apart from the device isolation region, and The above first bit line is, A line portion extending in the first horizontal direction; and A semiconductor device comprising a contact portion disposed below the above-mentioned line portion and connected to the second region of the above-mentioned first active portion.
  8. In Article 7, Including an insulating pattern, Each of the above gate structures includes a gate electrode, a gate capping pattern on the gate electrode, and a gate dielectric layer covering the side and bottom surfaces of the gate electrode, and In each of the above active regions, the first active portion and the second active portion are separated from each other by one of the gate structures, and The gate structures include a first gate structure that crosses the first active region and is adjacent to the first active portion of the first active region, and The insulating pattern is disposed between the gate capping pattern of the first gate structure and the second region of the first active portion of the first active region, and A semiconductor device comprising a contact portion of the first bit line that contacts the upper surface of the second region of the first active portion of the first active region and a portion that contacts the upper surface of the insulating pattern.
  9. In Article 7, In addition to insulating spacers, The above insulating spacer is, A contact spacer on the side of the second region of the first active portion and on the side of the contact portion; and A semiconductor device including a line spacer on the side of the above-mentioned line portion.
  10. In Article 7, A semiconductor device having a side of the first active portion having a fold portion between the side of the first region and the side of the second region.

Description

Semiconductor device including active portion and bit line The present invention relates to a semiconductor device comprising an active portion and a bit line, and a method for forming a semiconductor device. Research is underway to reduce the size of the components constituting semiconductor devices and improve their performance. For example, in DRAM, research is being conducted to reliably and stably form reduced-size components. FIGS. 1a, FIGS. 1b, FIGS. 2a, FIGS. 2b, and FIGS. 3 are drawings showing a semiconductor device according to an embodiment of the present invention. FIGS. 4a and FIGS. 4b are drawings showing a semiconductor device according to one embodiment of the present invention. FIGS. 5A and FIGS. 5B are drawings showing a semiconductor device according to one embodiment of the present invention. FIGS. 6a and FIGS. 6b are drawings showing a semiconductor device according to one embodiment of the present invention. FIGS. 7 to 16 are drawings illustrating an example of a method for forming a semiconductor device according to an embodiment of the present invention. In the following, terms such as "upper," "middle," and "lower" may be replaced with other terms, such as "first," "second," and "third," to describe the components of the specification. While terms such as "first," "second," and "third" may be used to describe various components, the components are not limited by these terms, and "first component" may be named "second component." In the drawings, reference numerals of the form BL (BL1), BL (BL2), etc., may be described as follows: a component designated as "BL" includes a component designated as "BL1" and a component designated as "BL2." The size ratio, width ratio, length ratio, etc., between the components depicted in the drawings can be understood from the components depicted in the drawings without separate explanation. An exemplary example of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1a, 1b, 2a, 2b, and 3. In FIGS. 1a, 1b, 2a, 2b, and 3, FIG. 1a is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 1b is a plan view showing a part of the component of FIG. 1a, FIG. 2a is a cross-sectional view showing an area taken along the line I-I' of FIG. 1, FIG. 2b is a partial enlarged view showing an area marked "A" in FIG. 2a, and FIG. 3 is a cross-sectional view showing an area taken along the line II-II' of FIG. 1a. Referring to FIGS. 1a, FIGS. 1b, FIGS. 2a, FIGS. 2b, and FIGS. 3, a semiconductor device (1) according to one embodiment may include a substrate (SUB), active regions (ACT), device isolation regions (STI), bit lines (BL), and insulating spacer structures (SP). The above substrate (SUB) may be a semiconductor substrate. The above substrate (SUB) may be provided as a bulk wafer, an epitaxial layer, a Silicon On Insulator (SOI) layer, or a Semiconductor On Insulator (SeOI) layer, etc. The above substrate (SUB) may include a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the above substrate (SUB) may be a substrate comprising at least one of silicon, silicon carbide, germanium, or silicon-germanium. For example, the above substrate (SUB) may be a single-crystal silicon substrate comprising a silicon material, for example, a single-crystal silicon material. The active regions (ACT) may be disposed on the substrate (SUB). The active regions (ACT) may be shaped to protrude in a vertical direction (Z) from the substrate (SUB). The active regions (ACT) may be formed of the same semiconductor material as the substrate (SUB), for example, single-crystal silicon. Each of the active regions (ACT) may be shaped like a bar extending in the D direction. The device isolation region (STI) may define the active regions (ACT) on the substrate (SUB). The device isolation region (STI) may be disposed on the sides of the active regions (ACT). The device isolation region (STI) may be disposed between the active regions (ACT). The device isolation region (STI) may be formed of an insulating material comprising at least one of silicon oxide and silicon nitride. The semiconductor device (1) may further include gate structures (GS) that extend across the active regions (ACT) and into the device isolation region (STI). The gate structures (GS) may be placed within gate trenches (GT) that extend across the active regions (ACT) and into the device isolation region (STI). Each of the gate structures (GS) may be in the shape of a line extending in the X direction. Each of the above gate structures (GS) may include a gate pattern (GP) and a gate capping layer (GC). Each of the above gate patterns (GP) may include a gate dielectric layer (Gox) and a gate electrode (GE). In each of the above gate structures (GS), the gate dielectric layer (Gox) may be disposed on the inner wall of the gate trench (GT), and the gate ele