KR-20260064250-A - IMAGE SENSOR

Abstract

An image sensor is provided. An image sensor according to some embodiments comprises a substrate including a first surface facing each other and a second surface, a separation pattern disposed within the substrate and defining a plurality of unit pixel regions, and a plurality of device separation patterns disposed within the substrate and defining an active region on the plurality of unit pixel regions, wherein the plurality of device separation patterns includes a plurality of first device separation patterns and a plurality of second device separation patterns, the depth of the second device separation pattern is greater than the depth of the first device separation pattern, the separation pattern penetrates the first device separation pattern, the unit pixel regions include a first unit pixel region, the first unit pixel region includes a first active region, and the first region included in the first active region is separated from the second region by a first sub-device separation pattern adjacent in a first direction and a second sub-device separation pattern adjacent in a second direction intersecting the first direction, and the first sub-device separation pattern is included in the second device separation pattern.

Inventors

• 하현지
• 윤선필

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241031

Claims (10)

1. A substrate comprising a first surface and a second surface facing each other; A separation pattern disposed within the substrate and defining a plurality of unit pixel regions; and It includes a plurality of device isolation patterns disposed within the substrate and defining an active region on the plurality of unit pixel regions, The above plurality of device isolation patterns includes a plurality of first device isolation patterns and a plurality of second device isolation patterns, and The depth of the second device isolation pattern is greater than the depth of the first device isolation pattern, and The above separation pattern penetrates the above first element separation pattern, and The above unit pixel regions include a first unit pixel region, and The above first unit pixel area includes a first active area, and A first region included in the first active region is separated from a second region by a first sub-element separation pattern adjacent in a first direction and a second sub-element separation pattern adjacent in a second direction intersecting the first direction, and The first sub-element isolation pattern is an image sensor included in the second element isolation pattern.
2. In paragraph 1, The above second region is an image sensor connected to ground.
3. In paragraph 1, An image sensor in which the minimum width of the first element isolation pattern is greater than the minimum width of the second element isolation pattern.
4. In paragraph 1, The above second sub-element isolation pattern is an image sensor included in the above second element isolation pattern.
5. In paragraph 1, The first device isolation pattern above includes a first liner layer, a second liner layer, and a gap filling layer, and An image sensor in which the second element isolation pattern is different from the first liner layer and includes the same material as the second liner layer.
6. In paragraph 5, The image sensor, wherein the second liner layer comprises any one of SiN, SiCN, and SiOCN.
7. A substrate comprising a first surface and a second surface facing each other; A separation pattern disposed within the above substrate and defining a plurality of unit pixel regions; A first device isolation pattern and a plurality of second device isolation patterns disposed within the substrate and defining an active region on the plurality of unit pixel regions, wherein The above separation pattern penetrates the above first element separation pattern, and The above unit pixel area includes a first unit pixel area separated by the above separation pattern, and From a planar perspective, the above-mentioned first unit pixel is, In the first direction, at least one of the second element isolation patterns adjacent to the impurity region is included, and It includes a gate electrode adjacent to the impurity region above, and An image sensor in which the depth of the second element isolation pattern is greater than the depth of the first element isolation pattern.
8. In Paragraph 7, An image sensor in which the minimum width of the first element isolation pattern is greater than the minimum width of the second element isolation pattern.
9. In Paragraph 7, The first device isolation pattern above includes a first liner layer, a second liner layer, and a gap filling layer, and An image sensor in which the second element isolation pattern is different from the first liner layer and includes the same material as the second liner layer.
10. In Paragraph 7, The image sensor, wherein the second element isolation pattern overlaps with the inclined surface of the gate electrode.

Description

Image Sensor The present invention relates to an image sensor. Image sensors may include charge coupled device (CCD) image sensors or CMOS image sensors. CMOS image sensors have a simple driving method and can integrate signal processing circuits onto a single chip, which enables product miniaturization. CMOS image sensors also have low power consumption, making them suitable for products with limited battery capacity. Furthermore, CMOS image sensors can utilize compatible CMOS process technologies, which can lower manufacturing costs. In addition, consumer demand for CMOS image sensors is increasing as high resolution becomes achievable with technological advancements. Figure 1 is a circuit diagram illustrating a unit pixel area of a pixel array. FIG. 2 is a plan view showing an image sensor according to embodiments. Figure 3 is a cross-section cut along the line I-I' of Figure 2. Figure 4 is an enlarged view of the M area of Figure 2. Figure 5 is a cross-sectional view taken along A-A' of Figure 4. Figure 6 is an enlarged view of the N region of Figure 5. FIGS. 7 to 17 are enlarged views illustrating the N region of FIG. 5, which is enlarged to explain a method for manufacturing an image sensor according to some embodiments. FIGS. 18 to 22 are enlarged views illustrating the N region of FIG. 5, which is enlarged to explain a method for manufacturing an image sensor according to some embodiments. FIGS. 23 to 28 are enlarged views illustrating the N region of FIG. 5, which is enlarged to explain a method for manufacturing an image sensor according to some embodiments. Figure 29 is an enlarged view of the M area of Figure 2. Figure 30 is a cross-sectional view taken along B-B' of Figure 29. Figure 31 is an enlarged view of the M area of Figure 2. Fig. 32 is a cross-sectional view taken along D-D' of Fig. 31. Fig. 33 is a cross-sectional view taken along E-E' of Fig. 31. Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1 is a circuit diagram illustrating a unit pixel area of a pixel array. For reference, FIG. 1 may be a 4T structure of a unit pixel area constituting a pixel array. Referring to FIG. 1, the pixel array may include a photoelectric conversion region (PD), a transfer transistor (TX), a floating diffusion region (FD), a reset transistor (RX), a source follower transistor (SX), and a select transistor (AX). The photoelectric conversion region (PD) can generate charge in proportion to the amount of light incident from the outside. The photoelectric conversion region (PD) may be a photodiode comprising an n-type impurity region and a p-type impurity region. The photoelectric conversion region (PD) may be coupled with a transfer transistor (TX) that transfers the generated and accumulated charge to a floating diffusion region (FD). The floating diffusion region (FD) is a region that converts charge into voltage, and because it has parasitic capacitance, charge can be accumulated and stored. One end of the transfer transistor (TX) may be connected to one of the photoelectric conversion regions (PD), and the other end of the transfer transistor (TX) may be connected to a floating diffusion region (FD). The transfer transistor (TX) may be formed as a transistor driven by a predetermined bias, for example, transfer signals. The transfer signals may be applied through a transfer gate (TG). The transfer gate (TG) may be a vertical transfer gate (VTG). The transfer transistor (TX) may transfer charges generated from the photoelectric conversion region (PD) to the floating diffusion region (FD) according to the transfer signals. The source follower transistor (SX) can amplify the change in the electrical potential of the floating diffusion region (FD), which receives charge from the photoelectric conversion region (PD), and output it to the output line (V OUT ). When the source follower transistor (SX) is turned on, a predetermined electrical potential, such as a power supply voltage (V DD ), provided at the drain of the source follower transistor (SX) can be transferred to the drain region of the select transistor (AX). The source follower gate (SF) of the source follower transistor (SX) can be connected to the floating diffusion region (FD). The select transistor (AX) can select a unit pixel area to be read row by row. The select transistor (AX) may be composed of a transistor driven by a select line that applies a predetermined bias, for example, a row selection signal. The row selection signal may be applied through a select gate (SEL). A reset transistor (RX) can periodically reset a floating diffusion region (FD). The reset transistor (RX) may be a transistor driven by a reset line that applies a predetermined bias, for example, a reset signal. The reset signal may be applied through a reset gate (RG). When the