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KR-20260064258-A - SEMICONDUCTOR DEDVICE AND METHOD FOR FABRICATING THE SAME

KR20260064258AKR 20260064258 AKR20260064258 AKR 20260064258AKR-20260064258-A

Abstract

A semiconductor device according to one embodiment of the present invention includes a bit line extending in a first direction, a first gate extending in a second direction, a second gate extending parallel to the first gate, an active region including a vertical portion located between the first gate and the second gate, and a first gate insulating layer located between the first gate and the vertical portion, wherein the active region includes a horizontal portion in contact with the bit line and the vertical portion, and the first gate insulating layer includes a lower gate insulating layer in contact with the first gate and an upper gate insulating layer in contact with the vertical portion, and the dielectric constant of the upper gate insulating layer may be greater than the dielectric constant of the lower gate insulating layer.

Inventors

  • 김세현

Assignees

  • 에스케이하이닉스 주식회사

Dates

Publication Date
20260507
Application Date
20241031

Claims (19)

  1. A bit line extending in the first direction; A first gate extending in a second direction; A second gate extending parallel to the first gate; An active region including a vertical portion located between the first gate and the second gate; and It includes a first gate insulating layer located between the first gate and the vertical portion, and The above active region includes the bit line and a horizontal portion in contact with the vertical portion, and The first gate insulating layer comprises a lower gate insulating layer in contact with the first gate and an upper gate insulating layer in contact with the vertical portion, and A semiconductor device in which the dielectric constant of the upper gate insulating layer is greater than the dielectric constant of the lower gate insulating layer.
  2. In Article 1, A semiconductor device further comprising a second gate insulating layer located between the second gate and the active region.
  3. In Article 1, The above active region comprises an indium gallium zinc oxygen semiconductor, and the semiconductor device in which a channel region is formed.
  4. In Article 1, A semiconductor device further comprising a first contact area located on the other side of the vertical portion and a second contact area that overlaps the first contact area.
  5. In Paragraph 4, The first contact area above includes the same material as the active area, and The above second contact region is a semiconductor device comprising at least one of a metal, a metal silicide, or a metal nitride.
  6. In Paragraph 4, A semiconductor device further comprising a capacitor overlapping the second contact area.
  7. In Article 1, The first gate is a semiconductor device that receives a control signal different from the second gate.
  8. In Article 1, A semiconductor device wherein the lower gate insulating layer comprises silicon oxide, and the upper gate insulating layer comprises at least one of hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide.
  9. A bit line extending in the first direction; A first gate extending in a second direction perpendicular to the first direction; A pair of second gates located on both sides of the first gate and extending parallel to the first gate; An active region comprising a vertical portion located between one of the pair of second gates and the first gate; and It includes a first gate insulating layer located between the first gate and the active region, and The above active region includes a horizontal portion that is in contact with one side of the vertical portion and extends in the first direction, and The first gate insulating layer comprises a lower gate insulating layer in contact with the first gate and an upper gate insulating layer in contact with the vertical portion, and A semiconductor device in which the dielectric constant of the upper gate insulating layer is greater than the dielectric constant of the lower gate insulating layer.
  10. In Article 9, The above bit line is a semiconductor device in contact with the above horizontal portion.
  11. In Article 9, A semiconductor device further comprising a second gate insulating layer located between the second gate and the active region.
  12. In Article 9, The above active region is a semiconductor device comprising an amorphous indium gallium zinc oxygen semiconductor.
  13. In Article 9, A semiconductor device further comprising a first contact area located on the other side of the vertical portion and a second contact area that overlaps the first contact area.
  14. In Article 13, The first contact area above includes the same material as the active area, and The above second contact region is a semiconductor device comprising at least one of a metal, a metal silicide, or a metal nitride.
  15. In Article 14, A semiconductor device further comprising a capacitor overlapping the second contact area.
  16. In Article 9, A semiconductor device wherein the lower gate insulating layer comprises silicon oxide, and the upper gate insulating layer comprises at least one of hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide.
  17. A bit line extending in a first direction is formed within the substrate, and A first gate is formed on the upper part of the bit line, extending in a second direction perpendicular to the first direction, and A first gate insulating layer in contact with the first gate is formed, and An active region is formed including a vertical portion extending along the sidewall of the first gate insulating layer and a horizontal portion in contact with the bit line, and A second gate insulating layer in contact with the above active region is formed, and A second gate is formed in contact with the second gate insulating layer, and Forming the first gate insulating layer above is, A lower gate insulating layer in contact with the first gate is formed, and It includes forming an upper gate insulating layer located on top of the lower gate insulating layer, and A method for manufacturing a semiconductor device in which the dielectric constant of the upper gate insulating layer is greater than the dielectric constant of the lower gate insulating layer.
  18. In Article 17, A method for manufacturing a semiconductor device comprising an amorphous indium gallium zinc oxygen semiconductor in the above active region.
  19. In Article 17, A method for manufacturing a semiconductor device in which the lower gate insulating layer comprises silicon oxide, and the upper gate insulating layer comprises at least one of hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide.

Description

Semiconductor Device and Method for Manufacturing the Same The present invention relates to a semiconductor device, and more specifically, to a semiconductor device having a memory cell. As miniaturization and increased integration density of semiconductor devices have emerged as major challenges, memory cells included in semiconductor devices can be formed to have a three-dimensional pattern. Miniaturized memory cells having a three-dimensional pattern can have configurations that improve the operational characteristics of the memory cells. FIG. 1 is a schematic perspective view of a semiconductor device according to one embodiment of the present disclosure. FIG. 2a is a cross-sectional view taken according to one embodiment of the present disclosure, in which the center of the first gate is cut by a cutting line parallel to the second direction. FIG. 2b is a cross-sectional view taken according to one embodiment of the present disclosure, in which the center of the second gate is cut by a cutting line parallel to the second direction. FIG. 2c is a cross-sectional view taken according to one embodiment of the present disclosure, in which the center of the bit line is cut by a cutting line parallel to the first direction. FIGS. 3a to 3c are for illustrating a method of forming a bit line including a semiconductor device according to one embodiment of the present disclosure. FIGS. 4a to 4c are for illustrating a method of forming a first gate included in a semiconductor device according to one embodiment of the present disclosure. FIGS. 5a to 5c and 6a to 6c are for illustrating a method of forming a bottom gate insulating layer included in a semiconductor device according to one embodiment of the present disclosure. FIGS. 7a to 7c and 8a to 8c are for illustrating a method of forming an upper gate insulating layer included in a semiconductor device according to one embodiment of the present disclosure. FIGS. 9a to 9c are for illustrating a method for forming an active region included in a semiconductor device according to one embodiment of the present disclosure. FIGS. 10a to 10c are for explaining a method for forming a second gate insulating layer included in a semiconductor device according to one embodiment of the present disclosure. FIGS. 11a to 11c are for illustrating a method of forming a second gate included in a semiconductor device according to one embodiment of the present disclosure. FIGS. 12a to 12c and FIGS. 13a to 13c are intended to explain a method for forming a capacitor included in a semiconductor device according to one embodiment of the present disclosure. Hereinafter, various embodiments of the present invention are described with reference to the accompanying drawings. The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this is not intended to limit the present invention to specific embodiments. The present invention is not limited to the embodiments but can be implemented in various different forms and should be understood to include various modifications, equivalents, and/or alternatives of the embodiments of the present invention. In addition, it should be noted that when assigning reference numerals to the components of each drawing, the same components are to have the same numeral whenever possible, even if they are shown in different drawings. In describing embodiments of the present invention, if it is determined that a detailed description of related known configurations or functions would hinder understanding of the embodiments of the present invention, such detailed description is omitted. In the specification, the singular form includes the plural form unless specifically stated otherwise in the text. As used in the specification, ‘comprises’ and/or ‘comprising’ do not exclude the presence or addition of one or more other components, steps, actions, and/or elements to the mentioned components, steps, actions, and/or elements. Hereinafter, a semiconductor device and a method for manufacturing the same according to embodiments of the present disclosure will be described with reference to the drawings. FIG. 1 is a schematic perspective view of a semiconductor device according to one embodiment of the present disclosure. Referring to FIG. 1, a semiconductor device (1) may include a substrate (LS) and may include a memory cell array (MCA) formed on the substrate (LS). The memory cell array (MCA) may include a plurality of memory cells (MC) that are repeatedly arranged on the substrate (LS). According to the embodiment, each memory cell (MC) may have a three-dimensional structure. More specifically, individual memory cells (MC) included in the memory cell array (MCA) may include a bit line (BL), a transistor (TR), and a capacitor (CAP). A bit line (BL) may be located within a substrate (LS) and may extend along a firs