KR-20260064262-A - METHOD FOR ALIGNING WAFER

Abstract

The wafer alignment method of the present disclosure may include the steps of setting a shot layout of a wafer as a unit pattern, repeatedly arranging the unit pattern to form a repeating pattern, setting at least some of the repeating pattern as an alignment key, loading the wafer, and aligning the wafer based on the alignment key.

Inventors

• 김재은
• 임동철
• 신경선
• 유지우

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241031

Claims (10)

1. Step of setting the wafer shot layout into a unit pattern; A step of forming a repeating pattern by repeatedly arranging the above unit pattern; A step of setting at least some of the above repeating patterns as alignment keys; A step of loading the wafer; and A step of aligning the wafer based on the above alignment key A wafer alignment method including
2. In Article 1, A wafer alignment method in which a portion of the alignment key is placed at the corner portion of the unit pattern.
3. In Article 2, The above unit patterns are provided in multiple numbers and arranged to be in contact with each other, and A wafer alignment method in which the above alignment key is formed at a position where the corner portions of each of the plurality of unit patterns come into contact with each other.
4. In Article 2, A wafer alignment method in which the above alignment key is located at the center of the above repeating pattern.
5. In Article 2, The above unit pattern is a first unit pattern, having a length in a first direction and a length in a second direction perpendicular to the first direction, The step of forming a repeating pattern by repeatedly arranging the above unit pattern is, A wafer alignment method comprising the step of forming a second unit pattern by moving the first unit pattern by the length of the first direction.
6. In Article 5, The step of forming a repeating pattern by repeatedly arranging the above unit pattern is, A wafer alignment method further comprising the step of forming a third unit pattern by moving the first unit pattern by the length of the second direction.
7. In Article 6, The step of forming a repeating pattern by repeatedly arranging the above unit pattern is, A wafer alignment method further comprising the step of forming a fourth unit pattern by moving the first unit pattern by the length of the first direction and the length of the second direction.
8. In Article 2, The above unit pattern is a first unit pattern, and The step of forming a repeating pattern by repeating the above unit pattern is, A wafer alignment method comprising the step of rotating the first unit pattern to form second to fourth unit patterns.
9. In Article 2, The above unit pattern is a first unit pattern, and The step of forming a repeating pattern by repeating the above unit pattern is, A step of forming a second unit pattern by mirroring the first unit pattern; and A wafer alignment method comprising the step of forming a third unit pattern and a fourth unit pattern by mirroring the first unit pattern and the second unit pattern.
10. A step of preparing a shot layout of a wafer containing a chip; A step of forming a repeating pattern by moving and replicating the shot layout of the wafer; A step of setting some of the above repeating patterns as alignment keys; A step of loading the above wafer; A step of aligning the wafer based on the alignment key using an optical microscope; and Step of measuring the wafer using an electron microscope A wafer alignment method including

Description

Wafer Alignment Method The present disclosure relates to a wafer alignment method. Generally, to manufacture semiconductor devices, a series of processes such as deposition, photolithography, etching, ion implantation, and cleaning can be performed on a semiconductor wafer. Since semiconductor devices are manufactured by forming fine patterns on a wafer, precise processes may be required. Therefore, when manufacturing semiconductor devices, it is necessary to prevent wafer rotation and defocus phenomena in order to form precise patterns on the wafer. Alignment can be performed by methods such as aligning the wafer notch in a specific direction to ensure the wafer is aligned in the correct position, or by matching a specific pattern on the wafer with a model image. FIG. 1 is a plan view illustrating a wafer including a plurality of shot regions. Figure 2 is an enlarged view of a portion of Figure 1. FIG. 3 is a flowchart illustrating a wafer alignment method according to one embodiment of the present disclosure. FIGS. 4 to 7 are drawings for illustrating some steps of a wafer alignment method according to one embodiment of the present disclosure. FIG. 8 is an enlarged view of an alignment key according to one embodiment of the present disclosure. FIGS. 9 to 11 are drawings for illustrating some steps of a wafer alignment method according to one embodiment of the present disclosure. FIGS. 12 and FIGS. 13 are drawings for illustrating some steps of a wafer alignment method according to one embodiment of the present disclosure. FIG. 14 is a drawing illustrating a wafer alignment method according to one embodiment of the present disclosure. FIG. 15 is a drawing illustrating an electron microscope according to one embodiment of the present disclosure. A wafer alignment method according to some embodiments of the present disclosure will be described in detail below with reference to the drawings. FIG. 1 is a plan view illustrating a wafer including a plurality of shot regions. FIG. 2 is an enlarged view illustrating a portion of FIG. 1. Referring to FIG. 1, a semiconductor wafer (W) may be provided. For example, the semiconductor wafer (W) may include a silicon wafer. The semiconductor wafer (W) may include a plurality of chips (CR) arranged along a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) may intersect each other, for example, may be orthogonal. A wafer (W) may include a plurality of shot regions (100). A shot region (100) may be an area exposed by a single exposure process. A shot region (100) may include one chip (CR) or a plurality of chips (CR). A chip (CR) may be formed in a chip region. For example, a chip (CR) may constitute a memory device. A chip (CR) may constitute a non-volatile memory device. A chip (CR) may constitute, for example, any one of a non-volatile NAND-type Flash memory, PRAM, MRAM, ReRAM, FRAM, or NOR Flash memory. Additionally, a chip (CR) may constitute a volatile memory device, such as DRAM and SRAM, in which data is lost when the power is cut off. In another embodiment, the chip (CR) may be any one of a logic chip, a measurement device, a communication device, a digital signal processor (DSP), or a system-on-chip (SOC). A scribe lane (SLR) can be placed between multiple chips (CR). The scribe lane (SLR) can define an area where the chips (CR) are formed. The scribe lane (SLR) can extend between the chips (CR) to separate the chips (CR) from each other. The scribe lane (SLR) may be an area for separating the chips (CR) individually during a sawing process. A pattern may be formed on the shot area (100). For example, a pattern consisting of a part of a rectangle may be formed at the corner of the shot area (100). The pattern may include a first pattern (P1) perpendicular to the corner of the shot area (100) and a second pattern (P2) folded along the corner of the shot area (100). The first pattern (P1) and the second pattern (P2) may have different thicknesses. For example, the first pattern (P1) may be thicker than the second pattern (P2). Design information regarding a pattern formed on a wafer (W) may be stored in advance as layout information, for example, in the memory of a wafer alignment device or an external device. The layout is information readable in a program for a wafer alignment device and may have various formats. As layout information, a shot layout corresponding to each shot area (100) of the wafer (W) may be stored in advance. A shot layout (LP) corresponding to a shot area (100) having a relatively unique pattern formed at a corner can be selected. The shot layout (LP) may be a unit pattern for forming an alignment key to be described later. The shot layout (LP) may include layout information for a pattern formed in the shot area (100) of the wafer (W). For example, the shot layout (LP) may include layout information for a first pattern (P1) and a second pattern (P2). The shot layout (LP) may include layou