KR-20260064266-A - SEMICONDUCTOR MEMORY DEVICE

KR20260064266AKR 20260064266 AKR20260064266 AKR 20260064266AKR-20260064266-A

Abstract

A semiconductor memory device comprises a cell substrate, a mold structure including a plurality of gate electrodes stacked in a first direction on the cell substrate, a channel structure penetrating the mold structure in a first direction, and a cell bonding metal layer disposed on the lower part of the mold structure in a first direction, a peripheral circuit board, a peripheral circuit structure including a peripheral bonding metal layer connected to the cell bonding metal layer and located on the peripheral circuit board, and a peripheral circuit structure connected to the cell structure in a first direction at a bonding surface, wherein the cell bonding metal layer comprises a first cell bonding region including a plurality of first cell bonding metals disposed at a first interval along a second direction intersecting the first direction, and a second cell bonding region including a plurality of second cell bonding metals disposed at a second interval different from the first interval in a second direction, and the first cell bonding region and the second cell bonding region are alternately disposed along the second direction.

Inventors

박병곤
정재호
최봉현
오수식
박준범
신용준
오현석
윤태수

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20241031

Claims (10)

A cell structure comprising a cell substrate, a mold structure including a plurality of gate electrodes stacked in a first direction on the cell substrate, a channel structure penetrating the mold structure in the first direction, and a cell bonding metal layer disposed on the lower part of the mold structure in the first direction; and A peripheral circuit board, a peripheral bonding metal layer connected to the cell bonding metal layer and located on the peripheral circuit board, and a peripheral circuit structure connected to the cell structure at a bonding surface in the first direction; comprising The cell bonding metal layer above is, A first cell bonding region comprising a plurality of first cell bonding metals arranged at a first interval along a second direction intersecting the first direction, and It includes a second cell bonding region comprising a plurality of second cell bonding metals arranged in the second direction at a second interval different from the first interval, and A semiconductor memory device in which the first cell bonding region and the second cell bonding region are alternately arranged along the second direction.
In paragraph 1, The plurality of first cell bonding metals are electrically insulated from the channel structure, and A semiconductor memory device in which the plurality of second cell bonding metals are electrically insulated from the channel structure.
In paragraph 2, The above second interval is a semiconductor memory device smaller than the above first interval.
In paragraph 3, At least some of the plurality of second cell bonding metals mentioned above are, A semiconductor memory device arranged alternately along a third direction intersecting the first direction and the second direction.
In paragraph 2, The cell bonding metal layer above is, A semiconductor memory device further comprising a plurality of channel bonding metals disposed on the cell substrate and electrically connected to the channel structure.
In paragraph 2, The cell bonding metal layer above is, It further includes a third cell bonding region comprising a plurality of third cell bonding metals arranged in the second direction at a third interval different from the first interval, and A semiconductor memory device in which the first cell bonding region and the third cell bonding region are alternately arranged along a third direction that intersects the first direction and the second direction.
In paragraph 2, The cell bonding metal layer above is, It includes N second cell bonding regions arranged along the second direction, The plurality of second cell bonding metals disposed in the Nth second cell bonding region are, A semiconductor memory device arranged in a pattern signifying the Nth arrangement from the 1st second cell bonding region located at one end of the cell bonding metal layer along the second direction.
A cell structure comprising a cell substrate, a mold structure including a plurality of gate electrodes stacked in a first direction on the cell substrate, a channel structure penetrating the mold structure in the first direction, and a cell bonding metal layer disposed on the lower part of the mold structure in the first direction; and A peripheral circuit board, a peripheral bonding metal layer connected to the cell bonding metal layer and located on the peripheral circuit board, and a peripheral circuit structure connected to the cell structure at a bonding surface in the first direction; comprising The cell bonding metal layer above is, A first cell bonding region comprising a plurality of first cell bonding metals arranged at predetermined intervals along a second direction intersecting the first direction, and It includes a second cell bonding region comprising a plurality of second cell bonding metals arranged at predetermined intervals along the second direction, and The ratio of the area of the plurality of second cell bonding metals to the area of the second cell bonding region is smaller than the ratio of the area of the plurality of first cell bonding metals to the area of the first cell bonding region, and A semiconductor memory device in which the first cell bonding region and the second cell bonding region are alternately arranged along the second direction.
In paragraph 8, The plurality of first cell bonding metals are electrically insulated from the channel structure, and The plurality of second cell bonding metals are electrically insulated from the channel structure, and The cell bonding metal layer above is, A semiconductor memory device further comprising a plurality of channel bonding metals disposed on the cell substrate and electrically connected to the channel structure.
In Paragraph 9, The cell bonding metal layer above is, N second cell bonding regions arranged along the second direction, and It further includes a third cell bonding region comprising a plurality of third cell bonding metals electrically insulated from the channel structure, and The second cell bonding region and the third cell bonding region are alternately arranged along the first direction and the third direction intersecting the second direction, and The ratio of the area of the plurality of third cell bonding metals to the area of the third cell bonding region is smaller than the ratio of the area of the plurality of first cell bonding metals to the area of the first cell bonding region, and In the second cell bonding region where the Nth arrangement is made, the plurality of second cell bonding metals are, A semiconductor memory device arranged in a pattern signifying the Nth arrangement from the 1st second cell bonding region located at one end of the cell bonding metal layer along the second direction.

Description

Semiconductor Memory Device The present invention relates to a semiconductor memory device. As there is a demand for semiconductor memory devices capable of storing high-capacity data in electronic systems, methods to increase the data storage capacity of semiconductor memory devices are being studied. As one of the methods to increase the data storage capacity of semiconductor memory devices, a semiconductor memory device comprising memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. In order to increase the data storage capacity of semiconductor memory devices, manufacturing technology for semiconductor memory devices including three-dimensionally arranged memory cells, such as vertical flash memory devices (VNAND), is being actively researched recently. Semiconductor memory devices are evolving from a three-dimensional cell structure to a structure in which memory cells and peripheral circuits are vertically joined. When a defect occurs in a memory cell and/or peripheral circuit, the technology to locate the defect and resolve it is an important technology in the manufacturing of semiconductor memory devices. Therefore, there is a need for a reference point that can identify the location of defects in memory cells and peripheral circuits. FIG. 1 is an exemplary block diagram for illustrating a semiconductor memory device according to one embodiment. FIG. 2 is an exemplary circuit diagram for explaining a semiconductor memory device according to one embodiment. FIG. 3 is a schematic layout drawing for explaining a semiconductor memory device according to one embodiment. FIG. 4 is an exemplary drawing showing a cross-section of the AA portion of FIG. 3. FIG. 5 is an exemplary drawing illustrating a part of a semiconductor memory device according to one embodiment. Figure 6 is an exemplary drawing illustrating an enlarged view of the R region of Figure 5. FIG. 7 is an exemplary drawing illustrating a portion of the cell bonding metal layer of a semiconductor memory device according to one embodiment. FIG. 8 is an exemplary drawing illustrating a portion of a cell bonding metal layer of a semiconductor memory device according to one embodiment. FIGS. 9 to 15 are exemplary drawings illustrating intermediate steps for explaining a method for manufacturing a semiconductor memory device according to one embodiment. FIG. 16 is an exemplary drawing illustrating a cross-section of a portion of a semiconductor memory device according to one embodiment. FIG. 17 is an exemplary drawing for illustrating an electronic system including a semiconductor memory device according to one embodiment. FIG. 18 is an exemplary perspective view for illustrating an electronic system including a semiconductor memory device according to one embodiment. FIG. 19 is an exemplary drawing showing a cross-section along II of FIG. 18. Prior to the detailed description of the embodiments, terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings, but should be interpreted in a meaning and concept consistent with the technical spirit of this disclosure, based on the principle that the inventor may appropriately define the concept of the terms to best describe his invention. Accordingly, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of this disclosure and do not represent all of the technical spirit of this disclosure; therefore, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application. In the following description, singular expressions include plural expressions unless the context clearly indicates otherwise. Terms such as "comprising" or "constituting" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Additionally, terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms, and said terms may be used for the purpose of distinguishing one component from another. Within the scope of the technical spirit of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. Furthermore, in the drawings, the shapes and sizes of the components may be exaggerated to emphasize clear explanations. Furthermore, it should be noted in advance that expressions such as upper side, top, lower side, bottom, sid