KR-20260064307-A - MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

KR20260064307AKR 20260064307 AKR20260064307 AKR 20260064307AKR-20260064307-A

Abstract

The present invention relates to a method for manufacturing a semiconductor memory device, wherein the method for manufacturing a semiconductor memory device comprises the steps of: forming an insulating film; forming a pre-laminated structure by alternately arranging a plurality of first material films and a plurality of second material films one by one on the surface of the insulating film in a stacking direction toward which the surface of the insulating film faces; forming a mask pattern on the pre-laminated structure having a first opening, a second opening, and a plurality of grooves arranged around the first opening; forming a first hole and a second hole at different depths toward the insulating film in the stacking direction by etching the pre-laminated structure through the first opening and the second opening while the plurality of grooves are blocked; and etching the pre-laminated structure through the first hole and the second hole while the plurality of grooves, the first opening, and the second opening are open so that the first hole and the second hole extend toward the insulating film.

Inventors

양나영
곽노규
장정식
최석민
최원근

Assignees

에스케이하이닉스 주식회사

Dates

Publication Date: 20260507
Application Date: 20241031

Claims (14)

Step of forming a first insulating film; A step of forming a preliminary laminate by alternately arranging a plurality of second insulating films and a plurality of sacrificial films one by one on the surface of the first insulating film in a stacking direction toward the surface of the first insulating film; A step of forming a mask pattern having a plurality of first openings, a plurality of second openings, a plurality of third openings, and a plurality of grooves disposed around the plurality of first openings on the prefabricated laminate; A step of forming a first group of holes that expose the uppermost sacrificial film among the plurality of sacrificial films by etching the pre-laminated structure through the plurality of first openings, the plurality of second openings, and the plurality of third openings; A step of forming a plurality of holes of a second group, each corresponding individually to the plurality of first openings, the plurality of second openings, and the plurality of third openings, at different depths toward the first insulating film in the stacking direction by repeatedly performing an etching process on the pre-laminated body while the plurality of grooves are blocked; and A method for manufacturing a semiconductor memory device comprising the step of forming a third group of holes by etching the prefabricated laminate in a state where the plurality of grooves are opened and some of the plurality of holes of the second group are opened through the plurality of first openings and the plurality of second openings.
In Article 1, The etching depth of the pre-laminated structure toward the first insulating film is, A method for manufacturing a semiconductor memory device that is larger in the step of forming a plurality of holes of the third group than when the etching process for the above-mentioned pre-laminated body is repeated.
In Article 1, A method for manufacturing a semiconductor memory device in which, on a plane parallel to the surface of the first insulating film, each of the plurality of grooves is formed narrower than each of the plurality of first openings, the plurality of second openings, and the plurality of third openings.
In Article 1, Repeating the etching process for the pre-laminated body while the plurality of grooves are blocked includes at least two etching cycles. The above etching cycle is A step of forming a photoresist pattern on the mask pattern such that the plurality of grooves are filled and at least one first opening among the plurality of first openings, at least one second opening among the plurality of second openings, and at least one third opening among the plurality of third openings are opened; A step of etching the pre-laminated body using an etching process utilizing the photoresist pattern as an etching barrier so that at least one of the plurality of sacrificial films is penetrated; and A method for manufacturing a semiconductor memory device comprising the step of removing the above photoresist pattern.
In Article 1, The plurality of holes of the second group above include a plurality of first holes corresponding to the plurality of first openings, a plurality of second holes corresponding to the plurality of second openings, and a plurality of third holes corresponding to the plurality of third openings. In the above stacking direction, the plurality of first holes and the plurality of second holes are formed deeper toward the first insulating film than the plurality of third holes, and A method for manufacturing a semiconductor memory device in which, in the above stacking direction, the plurality of first holes are formed deeper toward the first insulating film than the plurality of second holes.
In Article 5, The step of forming a plurality of holes of the third group above A step of forming a photoresist pattern on the mask pattern such that the plurality of grooves, the plurality of first holes, and the plurality of second holes are opened and the plurality of third holes are filled; A step of etching the pre-laminated structure such that the lowest sacrificial film among the plurality of sacrificial films is exposed by an etching process using the above photoresist pattern as an etching barrier; and A method for manufacturing a semiconductor memory device comprising the step of removing the above photoresist pattern.
In Article 5, The above plurality of first openings include a first opening of a first group and a first opening of a second group, and The plurality of first holes include a first hole of a first group corresponding to a first opening of the first group and a first hole of a second group corresponding to a first opening of the second group and formed deeper toward the first insulating film than the first hole of the first group in the stacking direction. A method for manufacturing a semiconductor memory device in which the plurality of grooves are arranged in greater numbers around the first opening of the second group than around the first opening of the first group.
In Article 1, The step of forming the above mask pattern on the above pre-laminated body is, A step of forming a mask film on the above pre-laminated structure; A step of forming a photoresist pattern having the plurality of etching holes and the plurality of auxiliary holes on the mask film; and A method for manufacturing a semiconductor memory device comprising the step of forming the plurality of first openings corresponding to the plurality of etching holes, the plurality of second openings, and the plurality of third openings corresponding to the plurality of auxiliary holes by etching regions of the mask film corresponding to the plurality of etching holes and the plurality of auxiliary holes.
In Article 8, A method for manufacturing a semiconductor memory device in which, on a plane parallel to the surface of the first insulating film, the auxiliary holes are formed narrower than each of the plurality of etching holes.
In Article 8, A method for manufacturing a semiconductor memory device in which the top of each of the above auxiliary holes is spaced apart from the top of an adjacent etching hole among the plurality of etching holes.
In Article 8, A method for manufacturing a semiconductor memory device in which, while etching regions of the mask film corresponding to the plurality of etch holes and the plurality of auxiliary holes, the upper end of each of the plurality of auxiliary holes is connected to an adjacent etch hole among the plurality of etch holes.
In Article 8, While etching regions of the mask film corresponding to the plurality of etch holes and the plurality of auxiliary holes, Each of the above plurality of auxiliary holes and the corresponding etching hole among the above plurality of etching holes are connected to each other to form an expanded etching hole, and A method for manufacturing a semiconductor memory device in which the upper portion of each of the plurality of grooves is connected to an adjacent first opening among the plurality of first openings.
In Article 1, A step of filling each of the plurality of holes of the third group with a sacrificial pillar; A step of forming a slit penetrating the above-mentioned prefabricated laminate; A step of replacing the plurality of sacrificial films with the plurality of conductive films through the slit; A step of removing the plurality of sacrificial pillars so that the plurality of conductive films are exposed and the plurality of holes of the third group are opened; A step of forming a sidewall insulating film on the sidewall of each of the plurality of holes of the third group; and A method for manufacturing a semiconductor memory device, further comprising the step of forming a plurality of gate contact plugs inside a plurality of holes of a third group so as to be connected to each of the plurality of conductive films.
Step of forming an insulating film; A step of forming a preliminary laminate by alternately arranging a plurality of first material films and a plurality of second material films one by one on the surface of the insulating film in a stacking direction toward the surface of the insulating film; A step of forming a mask pattern having a first opening, a second opening, and a plurality of grooves arranged around the first opening on the prefabricated laminate; A step of forming a first hole and a second hole at different depths toward the insulating film in the stacking direction by etching the pre-laminated body through the first opening and the second opening while the plurality of grooves are blocked; and A method for manufacturing a semiconductor memory device comprising the step of etching the pre-laminated body through the first hole and the second hole while the plurality of grooves, the first opening, and the second opening are open, so that the first hole and the second hole are extended toward the insulating film.

Description

Manufacturing Method of Semiconductor Memory Device The present invention relates to a method for manufacturing a semiconductor memory device, and more specifically, to a method for manufacturing a three-dimensional semiconductor memory device. Semiconductor memory devices can be applied not only to small electronic devices but also to electronic systems in various fields such as automobiles, medical devices, and data centers. Accordingly, the demand for semiconductor memory devices is increasing. A semiconductor memory device includes memory cells for storing data. A three-dimensional semiconductor memory device includes a plurality of memory cells arranged in three dimensions, which is advantageous for increasing capacity compared to a two-dimensional semiconductor memory device. In a three-dimensional semiconductor memory device, the integration density of memory cells can be improved by increasing the number of stacked memory cells. As the number of stacked memory cells increases, the number of stacked conductive films connected to the memory cells also increases. The conductive films are individually connected to gate contact plugs and are electrically connected to peripheral circuits via the gate contact plugs. As the number of stacked conductive films increases, process stability decreases, and the operational reliability of the semiconductor memory device may decrease. FIG. 1 is a block diagram showing an electronic system including a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment of the present invention. FIGS. 3a and FIGS. 3b are drawings illustrating a semiconductor memory device according to embodiments of the present invention. FIGS. 4a and FIGS. 4b are a plan view and a cross-sectional view showing a semiconductor memory device according to an embodiment of the present invention. FIGS. 5A and 5B are a plan view and a cross-sectional view showing a pre-laminated body, a cell column, and a mask film according to an embodiment of the present invention. FIGS. 6a and FIGS. 6b are a plan view and a cross-sectional view showing a first photoresist pattern and a mask pattern according to an embodiment of the present invention. FIGS. 7a, FIGS. 7b, FIGS. 7c, FIGS. 7d, FIGS. 7e, and FIGS. 7f are cross-sectional views showing a plurality of holes and a plurality of sacrificial columns according to an embodiment of the present invention. FIGS. 8A and FIGS. 8B are a plan view and a cross-sectional view showing a gate stack according to an embodiment of the present invention. FIGS. 9a and 9b are cross-sectional views showing a plurality of contact holes and a plurality of contact pillars according to an embodiment of the present invention. FIGS. 10a and FIGS. 10b are a plan view and a cross-sectional view showing a first photoresist pattern and a mask pattern according to an embodiment of the present invention. FIG. 11 is a cross-sectional view showing a first photoresist pattern and a mask pattern according to an embodiment of the present invention. Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are illustrative of embodiments according to the concept of the present invention. Embodiments according to the concept of the present invention are not to be interpreted as being limited to the embodiments described in this specification or application, but can be modified in various ways and replaced with other equivalent embodiments. In the following description, terms such as "first," "second," etc., used to explain various components are used for the purpose of distinguishing one component from another, and the order or number of components is not limited by said terms. Furthermore, unless specifically limited, components expressed in the singular or plural are not interpreted as limiting the number of components. FIG. 1 is a block diagram showing an electronic system including a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, the electronic system (1000) may be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system (1000) may include a host (1100) and a storage device (1200). The host (1100) can store data in the storage device (1200) or read data stored in the storage device (1200) based on the interface. The interface may include one or more of the following: a DDR (Double Data Rate) interface, a USB (Universal Serial Bus) interface, a MMC (multimedia card) interface, an eMMC (embedded MMC) interface, a PCI (peripheral component interconnection) interface, a PCI-E (PCI-express) interface, an ATA (Advanced Technology Attachment) interface, a Serial-ATA interface, a Parallel-ATA interface, a SCSI (small computer system inter