KR-20260064318-A - Semiconductor devices including multiple dies

Abstract

A semiconductor device comprises a plurality of dies stacked in a vertical direction, wherein each of the plurality of dies includes: a first substrate; a cell capacitor disposed on the first substrate; a cell transistor disposed on the cell capacitor; a second substrate disposed at a vertical level higher than the cell transistor; a peripheral circuit transistor disposed on the second substrate; and a through via extending in the vertical direction through the first substrate and the second substrate.

Inventors

• 강필규
• 박재화
• 문광진
• 김은미
• 이찬미

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241031

Claims (20)

1. A semiconductor device comprising a plurality of dies stacked in a vertical direction, Each of the above plurality of dies is, First substrate; A cell capacitor disposed on the first substrate; A cell transistor disposed on the cell capacitor above; A second substrate positioned at a vertical level higher than the cell transistor above; Peripheral circuit transistor disposed on the second substrate; A semiconductor device characterized by including a through via extending in the vertical direction through the first substrate and the second substrate.
2. In paragraph 1, Each of the above plurality of dies is, A wiring pattern disposed at a vertical level higher than the peripheral circuit transistor, wherein at least a portion of the wiring pattern is disposed at a position that vertically overlaps with the through-via; A front pad disposed on the upper surface of the above wiring pattern; and A semiconductor device characterized by further including a rear pad disposed on the lower surface of the above-mentioned through-via.
3. In paragraph 2, The plurality of dies above include a first die and a second die disposed on the second die, and The first die above includes a first through-via and a first front pad, and The second die includes a second through-via and a second rear pad, and A semiconductor device characterized in that the second die is disposed on the upper surface of the first die so that the second rear pad is attached to the first front pad, and the first through-via and the second through-via are electrically connected to each other.
4. In paragraph 2, Each of the above plurality of dies is, A front insulating layer having an upper surface disposed on the upper surface of the wiring pattern and disposed in the same plane as the upper surface of the front pad; and It includes a rear insulating layer disposed on the bottom surface of the second substrate and having a bottom surface disposed in the same plane as the bottom surface of the rear pad, The plurality of dies above include a first die and a second die disposed on the second die, and A semiconductor device characterized in that the upper surface of the first front insulating layer of the first die and the bottom surface of the second rear insulating layer of the second die are in contact with each other.
5. In paragraph 2, Each of the above plurality of dies is, A semiconductor device characterized by further including a through-via contact extending in the vertical direction within a via hole penetrating the second substrate and electrically connecting the peripheral circuit transistor and the cell transistor.
6. In paragraph 1, The above cell transistor is, A channel layer extending in the vertical direction above; A word line disposed on one side wall of the channel layer and extending in a first horizontal direction; and A semiconductor device characterized by including a bit line disposed on the upper surface of the channel layer and extending in a second horizontal direction intersecting the first horizontal direction.
7. In paragraph 6, A semiconductor device characterized in that the above channel layer comprises silicon, germanium, silicon germanium, or oxide semiconductor.
8. In paragraph 1, Each of the above plurality of dies is, It includes a through-via insulating layer surrounding the sidewall of the above-mentioned through-via, and The first substrate includes a first through-via hole penetrating the first substrate, and The second substrate includes a second through-via hole that penetrates the second substrate and is positioned at a location that vertically overlaps with the first through-via hole, and A semiconductor device characterized in that the through via is positioned to vertically overlap the first through via hole and the second through via hole.
9. In paragraph 8, The above through-via has an upper surface positioned at a vertical level higher than the upper surface of the first substrate, A semiconductor device characterized in that the above-mentioned through-via has a bottom surface positioned at a vertical level lower than the bottom surface of the second substrate.
10. In paragraph 8, The above through-via insulating layer has an upper surface disposed at a vertical level higher than the upper surface of the first substrate, A semiconductor device characterized in that the above-described through-via insulating layer has a bottom surface positioned at a vertical level lower than the bottom surface of the second substrate.
11. In paragraph 8, A first portion of the through-via insulating layer is disposed between the side wall of the through-via and the inner wall of the first through-via hole, and A second portion of the through-via insulating layer is disposed between the side wall of the through-via and the inner wall of the second through-via hole, and A semiconductor device characterized in that the through-via is electrically insulated from the first substrate or the second substrate.
12. In paragraph 8, Each of the above plurality of dies is, It further includes a buried insulating layer disposed between the first substrate and the second substrate and covering the cell transistor, and The entire sidewall of the above-mentioned through-via is covered by the through-via insulating layer, and A semiconductor device characterized in that at least a portion of the sidewall of the through-via insulating layer contacts the buried insulating layer.
13. First die; A semiconductor device comprising a second die disposed on the first die; Each of the above first die and the above second die is, First substrate; A cell capacitor disposed on the first substrate; A cell transistor disposed on the cell capacitor above; A second substrate positioned at a vertical level higher than the cell transistor above; Peripheral circuit transistor disposed on the second substrate; A through-via extending in the vertical direction through the first substrate and the second substrate; A wiring pattern disposed at a vertical level higher than the peripheral circuit transistor, wherein at least a portion of the wiring pattern is disposed at a position that vertically overlaps with the through-via; A front pad disposed on the upper surface of the above wiring pattern; and A semiconductor device characterized by including a rear pad disposed on the lower surface of the above-mentioned through-via.
14. In Paragraph 13, Each of the above plurality of dies is, A front insulating layer having an upper surface disposed on the upper surface of the wiring pattern and disposed in the same plane as the upper surface of the front pad; A rear insulating layer disposed on the bottom surface of the second substrate and having a bottom surface disposed in the same plane as the bottom surface of the rear pad; and A semiconductor device characterized by further comprising a buried insulating layer disposed between the first substrate and the second substrate and covering the cell transistor, wherein at least a portion of the through-via penetrates the buried insulating layer.
15. In Paragraph 14, The rear pad of the second die contacts the front pad of the first die, and A semiconductor device characterized in that the bottom surface of the rear insulating layer of the second die contacts the upper surface of the front insulating layer of the first die.
16. In paragraph 15, A semiconductor device characterized in that the through-via of the first die and the through-via of the second die are electrically connected to each other.
17. In Paragraph 13, Each of the above first die and the above second die is, A semiconductor device characterized by further including a through-via contact extending in the vertical direction within a via hole penetrating the second substrate and electrically connecting the peripheral circuit transistor and the cell transistor.
18. In Paragraph 13, The above cell transistor is, A channel layer extending in the vertical direction as described above; A word line disposed on one side wall of the channel layer and extending in a first horizontal direction; and A semiconductor device characterized by including a bit line that is positioned at a vertical level higher than the channel layer and extends in a second horizontal direction intersecting the first horizontal direction.
19. A first substrate including a first through-via hole; A cell capacitor disposed on the first substrate; A cell transistor disposed on the cell capacitor above; A second substrate disposed at a vertical level higher than the cell transistor and including a second through-via hole at a position vertically overlapping with the first through-via hole; A peripheral circuit transistor disposed on the second substrate; A through-via contact extending in the vertical direction within a via hole penetrating the second substrate and electrically connecting the peripheral circuit transistor and the cell transistor; A through-via extending in a vertical direction through the first through-via hole and the second through-via hole; A through-via insulating layer disposed on the sidewall of the above-mentioned through-via; A wiring pattern disposed at a vertical level higher than the peripheral circuit transistor, wherein at least a portion of the wiring pattern is disposed at a position that vertically overlaps with the through-via; A front pad disposed on the upper surface of the above wiring pattern; A front insulating layer having an upper surface disposed on the upper surface of the wiring pattern and disposed in the same plane as the upper surface of the front pad; A rear pad disposed on the lower surface of the above-mentioned through via; and A semiconductor device comprising a rear insulating layer having a bottom surface disposed on the bottom surface of the second substrate and disposed in the same plane as the bottom surface of the rear pad.
20. In Paragraph 19, The above cell transistor is, A channel layer extending in the vertical direction above; A word line disposed on one side wall of the channel layer and extending in a first horizontal direction; and A semiconductor device characterized by including a bit line that is positioned at a vertical level higher than the channel layer and extends in a second horizontal direction intersecting the first horizontal direction.

Description

Semiconductor devices including multiple dies The technical concept of the present invention relates to a semiconductor device, and more specifically, to a semiconductor device having a stacked structure of a plurality of dies. To improve the performance and storage capacity of semiconductor devices, semiconductor devices having a structure in which multiple semiconductor dies are stacked are widely used. As semiconductor devices are downscaled, the size of DRAM devices is also being reduced, and in DRAM devices having a 1T-1C structure in which one capacitor is connected to one transistor, there is a problem where leakage current through the channel region becomes increasingly large. Therefore, a vertical channel transistor including a channel layer extending in the vertical direction has been proposed to reduce leakage current. FIG. 1 is a schematic diagram showing a semiconductor device according to exemplary embodiments. FIG. 2 is a perspective view schematically showing each semiconductor die of FIG. 1. Figure 3 is a cross-sectional view showing part A of Figure 1. Figure 4 is a cross-sectional view schematically showing the cell array region of Figure 2. FIG. 5 is a cross-sectional view schematically showing a cell array region according to exemplary embodiments. FIGS. 6 to 8, 9a, 9b, 10 to 21, 22a, and 22b are schematic diagrams illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIG. 1 is a schematic diagram showing a semiconductor device (1) according to exemplary embodiments. FIG. 2 is a perspective view schematically showing each semiconductor die (10) of FIG. 1. FIG. 3 is a cross-sectional view showing portion A of FIG. 1. FIG. 4 is a cross-sectional view schematically showing a cell array region (MCA) of FIG. 2. Referring to FIGS. 1 to 4, the semiconductor device (1) may include a plurality of semiconductor dies (10) stacked in a vertical direction (Z). Each of the plurality of semiconductor dies (10) may be positioned so as to overlap each other in the vertical direction (Z), and each of the plurality of semiconductor dies (10) may be electrically connected to each other. In exemplary embodiments, a plurality of semiconductor dies (10) may include memory chips and, for example, DRAM devices. In exemplary embodiments, a plurality of semiconductor dies (10) may be high bandwidth memory devices. In exemplary embodiments, a plurality of semiconductor dies (10) may not be placed on a buffer die, and the semiconductor device (1) may be a bufferless semiconductor device. In other exemplary embodiments, a plurality of semiconductor dies (10) may be attached to a buffer die, and the buffer die may include a logic chip. In exemplary embodiments, a plurality of semiconductor dies (10) may be attached to a portion of an interposer, and a logic chip may be mounted on another portion of the interposer. In exemplary embodiments, each of the plurality of semiconductor dies (10) may include a through-via (12) extending in a vertical direction (Z) through the die body (10M). Each of the plurality of semiconductor dies (10) may include a front pad (14P) provided on the top surface of each semiconductor die (10) and a rear pad (16P) provided on the bottom surface of each semiconductor die (10). In exemplary embodiments, the front pad (14P) and the rear pad (16P) may be electrically connected to the through-via (12). In exemplary embodiments, each of the plurality of semiconductor dies (10) may include a front insulating layer (14I) provided on the top surface of each semiconductor die (10) and a rear insulating layer (16I) provided on the bottom surface of each semiconductor die (10). The front insulating layer (14I) may be disposed on the top surface of the die body (10M) of the semiconductor die (10), and the front insulating layer (14I) may have a top surface disposed in the same plane as the top surface of the front pad (14P). The rear insulating layer (16I) may be disposed on the bottom surface of the die body (10M) of the semiconductor die (10), and the rear insulating layer (16I) may have a bottom surface disposed in the same plane as the bottom surface of the rear pad (16P). In exemplary embodiments, each of the plurality of semiconductor dies (10) may be attached or bonded to one another by a metal-oxide hybrid bonding method. In exemplary embodiments, a front pad (14P) included in one semiconductor die (10) may be in contact with a rear pad (16P) included in another semiconductor die (10) placed directly above the one semiconductor die (10), and a front insulating layer (14I) included in one semiconductor die (10) may be in contact with a rear insulating layer (16I) included in another semiconductor die (10) placed directly above the one semiconductor die (10). In exemplary embodiments, a plurality of semiconductor dies (10) may include a first die (C1), a second die (C2), a third die (C3), a fourth die (C4), a fifth die (C5), and a sixth die (C6) stacked i