KR-20260064336-A - SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE

Abstract

The present invention relates to a semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a cell pillar structure and a conductive film covering the external surface of the cell pillar structure. The external surface of the cell pillar structure may be arranged at different distances from the center point along a plurality of first axes and a plurality of second axes extending radially from the center point. The plurality of first axes and the plurality of second axes may be arranged alternately in a clockwise direction, and the cell pillar structure may include a plurality of channel portions and a separation structure extending between the plurality of channel portions from the center point.

Inventors

• 박미성
• 장정식
• 곽노규
• 박인수
• 양나영
• 최석민
• 최원근

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260507

Application Date

20241031

Claims (20)

1. A cell column structure extending in a stacking direction intersecting the XY plane, comprising an external surface spaced apart from the center point and intersecting a plurality of first axes and a plurality of second axes that extend radially from a center point in the XY plane and are alternately arranged in a clockwise direction; and It includes a plurality of conductive films spaced apart from each other in the stacking direction and covering the outer surface of the cell column structure, The above cell column structure is, A plurality of channel sections that are each intersected by the plurality of first axes and are curved, having a radius of curvature defined between a vertex that intersects the corresponding first axis among the plurality of first axes and a center point; A plurality of memory portions interposed between each of the plurality of conductive films and the plurality of channel portions; and It includes a separation structure interposed between the plurality of channel portions and extended toward the center point, A semiconductor memory device in which each of the plurality of channel portions comprises an end portion disposed at a first distance of 30% to 80% of the radius of curvature from the vertex in the extension direction of the corresponding first axis.
2. In Article 1, A semiconductor memory device in which the outer surface of the cell column structure includes a plurality of convex portions that intersect each of the plurality of first axes.
3. In Article 1, A semiconductor memory device in which the cell pillar structure is formed in an elliptical shape in the above XY plane.
4. In Article 1, A semiconductor memory device in which the outer surface of the cell column structure includes a plurality of concave portions that intersect each of the plurality of second axes.
5. In Article 1, The outer surface of the cell column structure is positioned at a second distance from the center point in the extension direction of each of the plurality of first axes, and is positioned at a third distance from the center point in the extension direction of each of the plurality of second axes, The above third distance is a semiconductor memory device smaller than the above second distance.
6. In Article 1, A semiconductor memory device further comprising a buffer pattern interposed between the inner wall of each of the plurality of channel portions facing the center point and the separation structure.
7. In Article 6, A semiconductor memory device further comprising a barrier pattern interposed between the above buffer pattern and the above separation structure.
8. In Article 7, The above barrier pattern is, A seed barrier pattern interposed between the above buffer pattern and the above separation structure; and A semiconductor memory device comprising a growth barrier pattern interposed between the seed barrier pattern and the separation structure.
9. In Article 1, Each of the above plurality of memory units is A blocking insulating film interposed between a corresponding channel portion among the plurality of channel portions and each of the plurality of conductive films; A data storage film interposed between the blocking insulating film and the corresponding channel portion; and A semiconductor memory device comprising a tunnel insulating film interposed between the data storage film and the corresponding channel portion.
10. In Article 9, The above separation structure is a semiconductor memory device extending along the plurality of second axes from the center point to penetrate the data storage film.
11. A step of forming a laminate comprising a plurality of material films arranged in a stacking direction extending in an XY plane and intersecting the XY plane; A step of forming a hole having a first inner wall spaced apart from the center point, which intersects a plurality of first axes and a plurality of second axes that extend radially from the center point in the XY plane and are alternately arranged in a clockwise direction by etching the above-described laminate; A step of forming a channel membrane having a second inner wall extending along the first inner wall and facing the center point; A step of forming a plurality of seed barrier patterns that extend along the second inner wall and are alternately arranged in the clockwise direction with the plurality of second axes; A step of selectively growing a plurality of growth barrier patterns toward the center point from a plurality of third inner walls of the plurality of seed barrier patterns so that a plurality of etching targets of the channel film intersecting the plurality of second axes are opened; and A method for manufacturing a semiconductor memory device comprising the step of forming a plurality of openings by removing the plurality of etching targets to penetrate the channel film.
12. In Article 11, A method for manufacturing a semiconductor memory device wherein the first inner wall comprises a plurality of convex portions that intersect each of the plurality of first axes.
13. In Article 11, A method for manufacturing a semiconductor memory device in which the hole is formed in an elliptical shape in the above XY plane.
14. In Article 11, A method for manufacturing a semiconductor memory device wherein the first inner wall comprises a plurality of concave portions that intersect each of the plurality of second axes.
15. In Article 11, A method for manufacturing a semiconductor memory device in which the intersection point of each of the plurality of first axes and the first inner wall is positioned further from the center point than the intersection point of each of the plurality of second axes and the first inner wall.
16. In Article 11, A step of forming a memory film extended along the first inner wall before forming the channel film; and A method for manufacturing a semiconductor memory device, further comprising the step of etching a plurality of regions of the memory film through the plurality of openings.
17. In Article 11, A method for manufacturing a semiconductor memory device in which each of the plurality of seed barrier patterns and the plurality of growth barrier patterns comprises silicon.
18. In Article 11, Before forming the above plurality of seed barrier patterns, A step of forming a buffer oxide film along the second inner wall; and The method further includes the step of forming a buffer nitride film along the surface of the buffer oxide film, and Before forming the above plurality of openings, A step of removing a plurality of regions of the buffer nitride film exposed between the plurality of growth barrier patterns so that a plurality of regions of the buffer oxide film are exposed; A step of removing the plurality of growth barrier patterns and the plurality of seed barrier patterns; and A method for manufacturing a semiconductor memory device further comprising the step of removing the plurality of exposed regions of the buffer oxide film.
19. In Article 11, A step of forming a buffer oxide film along the second inner wall before forming the plurality of seed barrier patterns; A step of removing a plurality of regions of the buffer oxide film exposed between the plurality of growth barrier patterns before forming the plurality of openings; and A method for manufacturing a semiconductor memory device, further comprising the step of forming a separation structure such that the space between the plurality of growth barrier patterns and the plurality of openings are filled.
20. In Article 11, A step of forming a buffer oxide film along the second inner wall before forming the plurality of seed barrier patterns; and A step of removing a plurality of regions of the buffer oxide film exposed between the plurality of growth barrier patterns before forming the plurality of openings; and A method for manufacturing a semiconductor memory device, further comprising the step of removing the plurality of growth barrier patterns and the plurality of seed barrier patterns after forming the plurality of openings.

Description

Semiconductor Memory Device and Manufacturing Method of the Semiconductor Memory Device The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device including a three-dimensional memory cell array and a method for manufacturing a semiconductor memory device. Semiconductor memory devices can be applied not only to small electronic devices but also to electronic systems in various fields such as automobiles, medical devices, and data centers. Accordingly, the demand for semiconductor memory devices is increasing. A semiconductor memory device includes a memory cell array, and the memory cell array includes a plurality of memory cells for storing data. Semiconductor memory devices are classified into two-dimensional semiconductor memory devices including a two-dimensional memory cell array and three-dimensional semiconductor memory devices including a three-dimensional memory cell array. Multiple memory cells of a 3D memory cell array are arranged in the X-axis, Y-axis, and Z-axis directions. Multiple memory cells of a 2D memory cell array are arranged in the X-axis and Y-axis directions. Due to these structural differences, a 3D memory cell array is advantageous for increasing the capacity of semiconductor memory devices compared to a 2D memory cell array. Multiple memory cells of a three-dimensional memory cell array can be divided into multiple memory cell strings defined by multiple cell pillar structures. Memory cells included in each memory cell string can be connected in series by channel membranes of the cell pillar structures. To improve the integration density of the memory cell strings, the channel membranes of the cell pillar structures can be divided into two or more channel sections. In this case, the operational reliability of the memory cell strings may be reduced. FIG. 1 is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment of the present invention. FIGS. 2a and 2b are drawings illustrating a semiconductor memory device according to embodiments of the present invention. FIG. 3 is a drawing showing a gate stack and a cell pillar structure according to an embodiment of the present invention. FIGS. 4a to 4c are cross-sectional views showing a doft semiconductor structure and a cell pillar structure according to embodiments of the present invention. FIGS. 5a, FIGS. 5b, FIGS. 6a, and FIGS. 6b are plan views showing cross-sections of a cell column structure according to embodiments of the present invention. FIGS. 7a and 7b are a cross-sectional view and a plan view, respectively, showing a laminate, a hole, and a film disposed inside the hole according to an embodiment of the present invention. FIGS. 8A and FIGS. 8B are plan views showing seed barrier patterns according to an embodiment of the present invention. FIGS. 9a to 9f are plan views showing growth barrier patterns, buffer patterns, channel portions, and memory portions according to embodiments of the present invention. FIGS. 10a and FIGS. 10b are a cross-sectional view and a plan view, respectively, showing a gate stack according to an embodiment of the present invention. FIG. 11 is a plan view showing seed barrier patterns according to an embodiment of the present invention. FIGS. 12a and FIGS. 12b are a cross-sectional view and a plan view, respectively, showing a laminate, a hole, and a film disposed inside the hole according to an embodiment of the present invention. FIGS. 13a to 13c are plan views showing channel portions, memory portions, and a conductive film according to an embodiment of the present invention. FIGS. 14a and FIGS. 14b are a cross-sectional view and a plan view, respectively, showing a laminate, a hole, and a film disposed inside the hole according to an embodiment of the present invention. FIGS. 15a to 15c are plan views showing channel sections and openings according to embodiments of the present invention. FIG. 16 is a plan view showing a laminate, a hole, and a film disposed inside the hole according to an embodiment of the present invention. FIG. 17 is a block diagram showing an electronic system according to an embodiment of the present invention. Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are illustrative of embodiments according to the concept of the present invention. Embodiments according to the concept of the present invention are not to be interpreted as being limited to the embodiments described in this specification or application, but can be modified in various ways and replaced with other equivalent embodiments. In the following description, terms such as "first," "second," etc., used to explain various components are used for the purpose of distinguishing one component from another, and the order or number of components is not limited by said terms. Furthermore, unless