KR-20260064455-A - BREAKDOWN MITIGATION FOR PROGRAMMABLE RESISTANCE MEMORY ELEMENT

Abstract

A technique for lowering the threshold voltage of a threshold switching selector in a programmable resistive memory cell. When a memory system controls a circuit to apply a voltage across a programmable resistive memory cell to lower the threshold voltage of a threshold switching selector in a programmable resistive memory cell, it applies a first control signal to the circuit to establish a first resistance of transistors in series with the programmable resistive memory cell, word line, and bit line. To read a selected programmable resistive memory, the memory system applies a second control signal to the circuit to establish a second resistance of the circuit in series with the programmable resistive memory cell, word line, and bit line. The second resistance is lower than the first resistance.

Inventors

• 라우다토, 마리오
• 보즈다그, 카드리예 데니즈
• 린, 마크
• 사엔스, 후안 피.
• 후사메딘, 디미트리

Assignees

• 샌디스크 테크놀로지스 아이엔씨.

Dates

Publication Date

20260507

Application Date

20250428

Priority Date

20241030

Claims (20)

1. As a device, A circuit portion configured to be connected to a selected programmable resistive memory cell within a cross-point array and to apply a voltage across it—the circuit portion comprises a plurality of transistors configured to be connected in series with the selected programmable resistive memory cell, a selected word line, and a selected bit line within the cross-point array—; and It includes one or more control circuits communicating with the above circuit, and the one or more control circuits, When controlling the circuit to apply a voltage across the selected programmable resistance memory cell to lower the threshold voltage of the threshold switching selector in the selected programmable resistance memory cell, a first control signal is applied to the circuit to establish a first resistance of the plurality of transistors in series with the selected programmable resistance memory cell, the selected word line, and the selected bit line; A device configured to apply a second control signal to a circuit to establish a second resistance of the circuit in series with the selected programmable resistance memory cell, the selected word line, and the selected bit line to detect the selected programmable resistance memory, wherein the second resistance is lower than the first resistance.
2. A device according to claim 1, wherein the first control signal and the second control signal are decoder address signals having different magnitudes.
3. In paragraph 1, the above one or more control circuits are, In a threshold switching selector threshold voltage lowering operation, the first control signal is applied to the control gate of a decoder transistor in the circuit to select the selected word line or the selected bit line in order to lower the threshold voltage of the threshold switching selector in the programmable resistor memory cell; A device configured to apply the second control signal to the control gate of the decoder transistor in the circuit portion to select the selected word line or the selected bit line in order to detect the selected programmable resistive memory cell in a read operation.
4. In paragraph 1, the above one or more control circuits are, An apparatus configured to apply a sequence of voltages across a selected programmable resistive memory cell to progressively lower the threshold voltage of a threshold switching selector in the programmable resistive memory cell, including progressively lowering the resistance of the plurality of transistors in series with the selected programmable resistive memory cell, the selected word line, and the selected bit line in a sequence of voltages.
5. A device according to claim 1, wherein the one or more control circuits are configured to apply the first control signal to the circuit portion to establish the first resistance of the plurality of transistors in a first fire operation.
6. A device according to claim 1, wherein the one or more control circuits are configured to apply the first control signal to the circuit portion to establish the first resistance of the plurality of transistors in a forming operation.
7. A device according to claim 1, wherein the one or more control circuits are configured to apply the first control signal to the circuit portion to establish the first resistance of the plurality of transistors in a cold start operation.
8. In claim 1, the device wherein the threshold switching selector includes an OTS (Ovonic Threshold Switch).
9. A device according to claim 1, wherein the programmable resistive memory element within the programmable resistive memory cell comprises a magnetoresistive random access memory (MRAM) element.
10. A method for operating memory having a cross-point array, A step of providing a first decoder address signal having a first magnitude to a control gate of a transistor in a decoder circuit to cause the decoder circuit to charge a voltage on a first selected conductive line in the cross-point array while the transistor has a first resistance during a threshold voltage drop operation of a threshold switching selector of a selected programmable resistance memory cell connected to a first selected conductive line; and A method comprising the step of providing a second decoder address signal having a second size to the control gate of a transistor in the decoder circuit to charge a voltage on the first selected conductive line in the cross-point array while the transistor has a second resistance during a read operation of the selected programmable resistance memory cell connected to the first selected conductive line, wherein the second resistance is lower than the first resistance.
11. In Paragraph 10, A method further comprising the step of applying a series of forming voltages to a selected programmable resistance memory cell during a threshold voltage drop operation, wherein the decoder circuit applies a series of forming voltages to a control gate of a transistor in the decoder circuit to charge a voltage on the first selected conductive phase while the transistor has progressively lower resistances with a series of forming voltages.
12. In paragraph 10, the above threshold voltage lowering operation is a first fire operation, method.
13. In paragraph 10, the above-mentioned threshold voltage lowering operation is a forming operation, method.
14. In paragraph 10, the above threshold voltage drop operation is a cold start operation, method.
15. As a memory system, A cross-bar array comprising a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of programmable resistive memory cells—each programmable resistive memory cell having a threshold switching selector in series with a programmable resistive memory element, and each programmable resistive memory cell is located at a cross-point between one of the first conductive lines and one of the second conductive lines—; A decoder circuit comprising a transistor having a control gate; and It includes one or more control circuits communicating with the cross-bar array and the decoder circuit, and the one or more control circuits, Applying a first voltage to the control gate of a transistor such that the transistor has a first resistance while the transistor delivers a first current to the selected first conductive line in the cross-bar array to charge a voltage on the selected first conductive line during the formation operation of a threshold switching selector in a selected programmable resistance memory cell connected to the selected first conductive line; A memory system configured to apply a second voltage to the control gate of a transistor such that the transistor has a second resistance while the transistor delivers a second current to the selected first conductive line in the cross-bar array to charge a voltage on the selected first conductive line during a read operation of the selected programmable resistance memory cell connected to the selected first conductive line, wherein the second resistance is lower than the first resistance.
16. In paragraph 15, the above memory system is, The above forming operation includes a sequence of progressively lower forming voltages applied across the selected programmable resistive memory cell to progressively lower the threshold voltage of the threshold switching selector in the selected programmable resistive memory cell; A memory system in which the above one or more control circuits are configured to change the magnitude of the first voltage applied to the transistor during the forming operation in order to progressively lower the resistance of the transistor in a sequence of progressively lower forming voltages.
17. In paragraph 15, the above memory system is, A memory system in which the first voltage and the second voltage are decoder address signals having different magnitudes.
18. In Clause 17, the above memory system is, A memory system in which the decoder circuit is a local word line decoder or a local word line decoder configured to select the selected first conductive line in response to the decoder address signals.
19. In paragraph 15, the above threshold switching selector includes an OTS (Ovonic Threshold Switch), in a memory system.
20. In paragraph 15, the memory system wherein the programmable resistive memory element comprises a magnetoresistive random access memory (MRAM) element.

Description

Breakdown Mitigation for Programmable Resistant Memory Element Memory is widely used in various electronic devices such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source, such as a battery. Non-volatile memory can be made non-volatile for at least a limited time by adding a battery to the power supply outside the memory chip. Memory cells can reside in a cross-point memory array. In a memory array having a cross-point type architecture, one set of conductive lines runs across the surface of the substrate, and another set of conductive lines is formed on top of another set of conductive lines running orthogonally to the initial layer. Memory cells are located at the cross-point junctions of the two sets of conductive lines. Cross-point memory arrays are sometimes referred to as cross-bar memory arrays. Programmable resistive memory cells are formed from materials having programmable resistance. In a binary approach, a programmable resistive memory cell can be programmed into one of two resistance states: a high resistance state (HRS) and a low resistance state (LRS). In some approaches, more than two resistance states may be used. One type of programmable resistive memory cell is a magnetoresistive random access memory (MRAM) cell. Unlike some other memory technologies that use electronic charges (DRAM) or voltages (SRAM) to store data, MRAM cells use magnetization to represent stored data. Bits of data are written to the MRAM cell by changing the magnetization direction of the magnetic elements ("free layer") within the MRAM cell, and bits are read by measuring the resistance of the MRAM cell, which changes according to the magnetization direction. However, cross-point memory arrays can have other types of memory cells. For example, a cross-point memory array can have memory cells of other technologies such as ReRam, PCM (Phase Change Memory), or FeRam. In a cross-point memory array, each memory cell may include a threshold switching selector in series with a material having a programmable resistor. The threshold switching selector has high resistance in the off or non-conductive state until it is biased to a voltage higher than the threshold voltage (Vt) or a current above the threshold current (It), and until that voltage bias drops below Vhold ("Voffset") or to a current below the holding current (Ihold). While Vhold is exceeded across the threshold switching selector after Vt is exceeded, the threshold switching selector has significantly lower resistance (in the on or conductive state). The threshold switching selector remains on until its current drops below the holding current (Ihold) or its voltage drops below the holding voltage (Vhold). When this occurs, the threshold switching selector returns to the off (higher) resistance state. To read a memory cell, the threshold switching selector is activated by turning on before the resistance state of the memory cell is determined. One example of a threshold switching selector is an Ovonic Threshold Switch (OTS). Other examples of threshold switching selectors include, but are not limited to, volatile conductive bridges (VCBs), metal-insulator-metal (MIMs), or other materials that provide a high degree of nonlinear dependence of current on the selected voltage. Elements with similar drawing numbers refer to common components in different drawings. FIG. 1 is a block diagram of an embodiment of a non-volatile memory system connected to a host. FIG. 2 is a block diagram of one embodiment of a memory die. FIG. 3 is a block diagram of one embodiment of an integrated memory assembly including a control die and a memory structure die. FIG. 4a depicts one embodiment of a part of a memory array forming a cross-point architecture in an oblique view. FIGS. 4b and 4c present a side view and a top view of the cross-point structure of FIG. 4a, respectively. FIG. 4d depicts an example of a part of a 2-level memory array forming a cross-point architecture in an oblique view. FIG. 5 illustrates an example of the structure of an MRAM memory cell, wherein, for example, a selected cell is driven by a current source to read or write. FIGS. 6a and 6b illustrate embodiments of the integration of critical switching selectors into an MRAM memory array having a cross-point architecture. FIG. 7a depicts an example of a memory array having a cross-point architecture accessed using a forced voltage approach. FIG. 7b depicts an example of a memory array having a cross-point architecture in which a current-force approach is used. FIG. 8 is a schematic diagram illustrating a resistor along a path that provides voltage across a programmable resistive memory cell. FIG. 9 is a graph i