KR-20260064470-A - SYSTEM AND METHOD FOR LOW-POWER DOUBLE DATA RATE (LPDDR) COMPATIBLE HIGH BANDWIDTH NAND (HBN)

Abstract

A system and method for a low-power dual data transfer rate (LPDDR) compatible high-bandwidth NAND (HBN) comprises the steps of: receiving a request related to a memory device from an application; issuing a first command to the memory device through a memory controller, wherein the request has a request type; polling the memory device for the state of the memory device, wherein the first command is based on the request type; determining that the memory device is ready based on the state, wherein the state is related to the readiness of the memory device for the request; and issuing a second command to the memory device through the memory controller to perform the request.

Inventors

• 리, 종왕
• 이호빈
• 양, 징
• 피추마니, 레카
• 기양석
• 정명준

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20250616

Priority Date

20250130

Claims (20)

1. Regarding the method: A step of receiving a request related to a memory device from an application; The above request has a request type, and A step of issuing a first command to the memory device through a memory controller; The above first command is based on the above request type, and A step of polling the memory device for the state of the memory device; The above state is related to the readiness of the memory device for the above request, and A step of determining that the memory device is prepared based on the above state; and A method comprising the step of issuing a second command to the memory device through the memory controller to perform the above request.
2. In Article 1, A method in which the memory controller includes a low-power double data rate (LPDDR) memory controller.
3. In Article 1, A method comprising a memory device including a high bandwidth flash NAND memory and a front-end controller configured to control the high bandwidth flash NAND memory based on commands from the LPDDR memory controller.
4. In Article 1, The above request type is a method that is a write request.
5. In Article 4, A method in which the state of the above memory device is based on the availability of space within the buffer of the above memory device.
6. In Article 5, A method further comprising the step of reserving a predetermined space within the buffer for the above application.
7. In Article 1, The above request type is a method that is a read request.
8. In Article 7, A method in which the state of the memory device is based on the availability of data related to the request within the buffer of the memory device.
9. In the system: Includes host, The above host is: Memory controller; Processing circuit; and It includes a memory connected to the above processing circuit, and The above memory stores instructions that cause the execution of a method when executed by the above processing circuit, and The above method is: A step of receiving a request related to a memory device from an application; The above request has a request type, and A step of issuing a first command to the memory device through a memory controller; The above first command is based on the above request type, and A step of polling the memory device for the state of the memory device; The above state is related to the readiness of the memory device for the above request, and A step of determining that the memory device is prepared based on the above state; and A system comprising the step of issuing a second command to the memory device through the memory controller to perform the above request.
10. In Article 9, The above memory controller is a system including a low-power double data rate (LPDDR) memory controller.
11. In Article 10, The memory device is a system comprising a high bandwidth flash NAND memory and a front-end controller configured to control the high bandwidth flash NAND memory based on commands from the LPDDR memory controller.
12. In Article 9, The above request type is a system related to write requests.
13. In Article 12, The state of the above memory device is a system based on the availability of space within the buffer of the above memory device.
14. In Article 13, The above method is: A system further comprising the step of reserving a predetermined space within the buffer for the above application.
15. In Article 9, The above request type is a read request system.
16. In Article 15, A system in which the state of the above memory device is based on the availability of data related to the request within the buffer of the above memory device.
17. Regarding memory devices: High bandwidth NAND (HBN); and It includes a front-end controller configured to control access to the above HBN, and The above front-end controller is: buffer; Processing circuit; and It includes a memory connected to the above processing circuit, and The above memory stores instructions that cause the execution of a method when executed by the above processing circuit, and The above method is: A step of receiving a first command from a memory controller of a host device; A step of determining that the state of the above buffer satisfies the condition related to the first command; A step of transmitting the state of the buffer to the memory controller; A step of receiving a second command from the memory controller; and A memory device comprising the step of executing an operation on the buffer based on the second command above.
18. In Article 17, The second command above is a read request for data stored in the HBN, and, The above condition is a memory device including the data being in the buffer.
19. In Article 17, The second command above is a write request for data stored in the HBN, and, The above condition is a memory device comprising having sufficient available space for the data in the buffer.
20. In Article 19, The above method is: A memory device further comprising the step of reserving a predetermined space within the buffer for the above data.

Description

System and Method for Low-Power Double Data Rate (LPDDR) Compatible High Bandwidth NAND (HBN) One or more aspects of the embodiments according to this description relate to computing systems, and more specifically to systems and methods for low-power dual data transfer rate compatible high-bandwidth flash. Some computing devices, such as mobile devices, can utilize low-power double data rate (LPDDR) SDRAM and are equipped with LPDDR memory controllers. High bandwidth flash (HBF) NAND memory devices can provide higher throughput but may not be compatible with LPDDR memory controllers. In light of this general technical environment, the aspects of this description are relevant. These and other features and advantages of the present description will be grasped and understood by referring to the description of the invention, the claims, and the accompanying drawings. FIG. 1 illustrates a block diagram of a system according to one or more embodiments of the present description. FIG. 2 illustrates a block diagram of a system having an LPDDR-compatible HBFHBN according to one or more embodiments of the present invention. FIG. 3 illustrates a timing graph of a read operation performed by a system having an LPDDR-compatible HBF according to one or more embodiments of the present invention. FIG. 4 illustrates a timing graph of a write operation performed by a system having an LPDDR compatible HBF according to one or more embodiments of the present invention. FIG. 5 illustrates a flowchart of a process interacting with a memory device through a host memory controller according to one or more embodiments of the present invention. FIG. 6 illustrates a flowchart of a process for executing a read request on a memory device through a host memory controller according to one or more embodiments of the present invention. FIG. 7 illustrates a flowchart of a process for executing a write request on a memory device through a host memory controller according to one or more embodiments of the present invention. FIGS. 8a and 8b illustrate a flowchart of a process in which a request received from a host memory controller is executed by a memory device according to one or more embodiments of the present invention. The detailed description disclosed below in conjunction with the attached drawings is intended to describe exemplary embodiments of a system and method for an LPDDR-compatible high-bandwidth NAND provided according to this description, and is not intended to represent the only form in which this description may be configured or utilized. The description discloses features of this description in connection with the exemplary embodiments. However, it should be understood that identical or equivalent functions and structures may be achieved by different embodiments intended to be included within the scope of this description. As indicated elsewhere in this specification, the same reference numerals are intended to denote the same elements or features. High Bandwidth NAND (HBN) is a type of NAND flash memory featuring a wide input/output (I/O) interface that provides more data channels (e.g., I/O lines) for faster communication with the memory controller and higher throughput. Due to its high bandwidth and throughput, HBN memory can improve the performance of mobile devices for high-throughput applications, such as large language model (LLM) applications and other artificial intelligence (AI) or machine learning (ML) applications. However, some mobile platforms utilize low-power double data rate (LPDDR) SDRAM interfaces for high-throughput applications, which are generally incompatible with HBN. For example, LPDDR memory controllers operate based on read and write latency, which can be shorter than the latency of HBN read and write operations. Therefore, if the LPDDR memory controller reads data directly from or writes data directly to the HBN, there are timing issues that can cause system problems. The present invention provides techniques for a memory device utilizing high bandwidth flash NAND (HBFNAND) memory to be compatible with an existing LPDDR memory controller. The memory device includes a front-end controller that facilitates interactions between the LPDDR memory controller and the HBN. In some embodiments, for read operations, the front-end controller preloads data from the HBN into a buffer so that the LPDDR memory controller can load data from the buffer instead of the HBN. This can reduce the read latency experienced by the LPDDR memory controller to an acceptable predetermined time. Similarly, for write operations, the front-end controller allocates space on the buffer so that the LPDDR memory controller can write data to the buffer instead of the HBN. Thus, the write latency experienced by the LPDDR is the time taken to write data to the buffer, which may be shorter than the latency of writing data to the HBN. These technologies allow HBN to be used in mobile devices with LPDDR memory controllers without changin