Search

KR-20260064513-A - Packaging Substrate

KR20260064513AKR 20260064513 AKR20260064513 AKR 20260064513AKR-20260064513-A

Abstract

The packaging substrate of the embodiment comprises a glass core; an upper redistribution layer; and a lower redistribution layer. The glass core is a plate-shaped glass having vias, the upper redistribution layer is a redistribution layer disposed on top of the glass core, and the lower redistribution layer is a redistribution layer disposed on bottom of the glass core. The redistribution layer includes a wiring layer and an insulating layer. The wiring layer is a patterned copper layer having grains, and an upper surface is located on top of the upper redistribution layer, and an electronic device is mounted on the upper surface. C is the area ratio of grains in the wiring layer disposed on the upper redistribution layer, where the ratio of the long axis to the short axis is 3:1 or greater, and D is the area ratio of grains in the wiring layer disposed on the lower redistribution layer, where the ratio of the long axis to the short axis is 3:1 or greater. The value obtained by dividing C of the packaging substrate by D is 0.85 or greater and 0.99 or less. An embodiment can provide a packaging substrate that improves signal integrity and reduces the occurrence of problems such as electromagnetic interference even during high-frequency signal transmission by controlling the crystal structure of copper placed in the wiring layer.

Inventors

  • 김성진
  • 김진철

Assignees

  • 앱솔릭스 인코포레이티드

Dates

Publication Date
20260507
Application Date
20250925
Priority Date
20241031

Claims (10)

  1. A packaging substrate comprising a glass core; an upper redistribution layer; and a lower redistribution layer, The above glass core is a plate-shaped glass with vias arranged therein, and The above upper redistribution layer is disposed on the upper part of the glass core, and The above lower redistribution layer is disposed below the glass core, and Each of the above upper redistribution layer and lower redistribution layer includes a wiring layer and an insulation layer, and The above wiring layer is a patterned copper layer having grains, and The above insulating layer is a layer comprising an insulating polymer resin or an insulating inorganic material, and An upper surface is located on the upper surface of the upper redistribution layer, and an electronic component is mounted on the upper surface. A lower surface facing the upper surface is located at the bottom of the lower distribution layer, and C is the area ratio of grains in which the ratio of the long axis to the short axis is 3:1 or greater in the wiring layer disposed in the upper wiring layer above, and D is the area ratio of grains in which the ratio of the long axis to the short axis is 3:1 or greater in the wiring layer disposed in the lower wiring layer above, and A packaging substrate in which the value obtained by dividing the C of the packaging substrate by the D is 0.85 or more and 0.99 or less.
  2. In paragraph 1, The copper layer comprises (111) direction-oriented grains, (200) direction-oriented grains, (220) direction-oriented grains, (211) direction-oriented grains and (310) direction-oriented grains, and TC is the sum of the area ratio of the (220) direction-oriented grain, the area ratio of the (211) direction-oriented grain, and the area ratio of the (310) direction-oriented grain, and TD is the sum of the area ratio of the (111) direction-oriented grain and the area ratio of the (200) direction-oriented grain, and A is the ratio of TD based on TC in the wiring layer disposed in the upper redistribution layer, and B is the ratio of TD based on TC in the wiring layer disposed in the lower redistribution layer, and A packaging substrate in which the value obtained by dividing the above A by the above B is 0.60 or more and 0.75 or less.
  3. In paragraph 1, A packaging substrate in which the average size of grains in the wiring layer disposed in the upper wiring layer is larger than the average size of grains in the wiring layer disposed in the lower wiring layer.
  4. In paragraph 1, A of the above packaging substrate is a packaging substrate in which A is 0.2 or greater.
  5. In paragraph 1, A packaging substrate having an average grain size of 0.45 μm or more and 0.48 μm or less in a wiring layer disposed on the upper redistribution layer.
  6. In paragraph 1, A packaging substrate having an average grain size of 0.50 μm or more and 0.53 μm or less in a wiring layer disposed on the lower redistribution layer.
  7. In paragraph 1, The above packaging substrate is a packaging substrate having an impedance of 49Ω or more and 52Ω or less.
  8. In paragraph 1, The above packaging substrate is a packaging substrate having an electrical conductivity of 5.0 x 10⁷ S/m or higher.
  9. In paragraph 1, The above packaging substrate is a packaging substrate having a reflection coefficient of 3.2% or less.
  10. In paragraph 1, The above packaging substrate is a packaging substrate having a signal delay of 80 pc or less.

Description

Packaging Substrate An embodiment relates to a packaging substrate with improved integrity and reliability of electrical signal transmission. In the production of electronic components, implementing circuits on a semiconductor wafer is called the front-end process (FE), and assembling the wafer into a state usable in an actual product is called the back-end process (BE), and the packaging process is included in the back-end process. The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. While semiconductor technology is evolving into various forms, such as sub-micron and nano-scale linewidths, over ten million cells, high-speed operation, and significant heat dissipation, the technology to perfectly package these technologies has not yet been sufficiently supported. Consequently, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections, rather than by the performance of the semiconductor technology itself. Ceramic or resin is used as the material for packaging substrates. In the case of ceramic substrates, it is difficult to mount high-performance, high-frequency semiconductor devices due to high resistance or dielectric constant. While resin substrates allow for the mounting of relatively high-performance, high-frequency semiconductor devices, there are limitations in reducing the wiring pitch. Recently, research is underway on applying glass substrates as packaging substrates for high-end applications. By forming through-holes in the glass substrate and applying conductive materials to these holes, the wiring length between the device and the motherboard can be shortened, and excellent electrical characteristics can be achieved. Related prior art includes Korean registered patent No. 10-2400616 and Korean published patent No. 10-2023-0154459. FIG. 1a is a drawing showing the EBSD Map of Example 1-1; FIG. 1b is a drawing showing the area ratio of grains in Example 1-1 where the long-short axis ratio is 3:1 or greater; FIG. 1c is a drawing showing the area ratio of each oriented grain of Example 1-1; FIG. 2a is a drawing showing the EBSD Map of Example 1-2; FIG. 2b is a drawing showing the area ratio of grains in Example 1-2 where the long-short axis ratio is 3:1 or greater; and FIG. 2c is a diagram showing the area ratio of each orientation grain in Examples 1-2. Hereinafter, embodiments are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Throughout the specification, similar parts are denoted by the same reference numerals. Throughout this specification, the term “combination thereof” included in the Markush-type expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-type expression, and means including one or more selected from the group consisting of said components. Throughout this specification, terms such as “first,” “second,” or “A,” “B” are used to distinguish identical terms from one another. Additionally, singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the “~” system may mean that the compound contains a compound corresponding to “~” or a derivative of “~”. In this specification, the meaning that B is located on A means that B is located in direct contact with A or that B is located on A with another layer located between them, and is not interpreted as being limited to B being located in contact with the surface of A. In this specification, the meaning of being connected to B on A means that A and B are directly connected or connected through other components between A and B, and unless otherwise specifically stated, it is not interpreted as being limited to a direct connection between A and B. In this specification, singular expressions are interpreted to include singular or plural forms as interpreted in context unless otherwise specified. In this specification, the shapes, relative sizes, angles, etc., of each component in the drawings are exemplary and may be exaggerated for illustrative purposes, and the rights are not interpreted as being limited to the drawings. In this specification, "A and B are adjacent" means that A and B are located in contact with each other, or that A and B are located close to each other even if they are not in contact. Unless otherwise specified, the expression "A and B are adjacent" in this specification is not interpreted as being limited to A and B being in contact with each other. Unless otherwise specified in this specif