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KR-20260064514-A - Packaging Substrate

KR20260064514AKR 20260064514 AKR20260064514 AKR 20260064514AKR-20260064514-A

Abstract

An embodiment relates to a packaging substrate in which thermal shock resistance, impact resistance, durability, reliability, etc. are improved by controlling the difference in physical properties between the upper and lower parts of a glass core. The packaging substrate of the embodiment comprises a glass core; a wiring layer; A packaging substrate comprising: a glass core and an insulating layer; wherein the glass core is a plate-shaped glass having vias disposed therein, the wiring layer is an electrically conductive layer disposed on the surface of the glass core, the insulating layer is a layer disposed in the space between the electrically conductive layers and comprising a mixture of a polymer resin and insulating particles, the packaging substrate has an upper surface on which a semiconductor device is mounted and a lower surface opposite thereto, the insulating layer disposed on the upper part of the glass core is an upper insulating layer, a cover layer is further disposed on the upper part of the upper insulating layer, the insulating layer disposed on the lower part of the glass core is a lower insulating layer, a solder resist layer is further disposed on the lower part of the lower insulating layer, the flexibility index FI is a value represented by Equation 1 below, and the FI of the cover layer has a value greater than the FI of the solder resist layer. [Equation 1] FI = 10,000 Х (E' Х tan δ) / (H Х Er) In Equation 1 above, E' is the storage modulus (GPa), tan δ is the loss tangent, H is the hardness (GPa), and Er is the damping modulus (GPa).

Inventors

  • 김성진
  • 김진철

Assignees

  • 앱솔릭스 인코포레이티드

Dates

Publication Date
20260507
Application Date
20250925
Priority Date
20241031

Claims (9)

  1. A packaging substrate comprising a glass core; a wiring layer; and an insulating layer, The above glass core is a plate-shaped glass with vias arranged therein, and The above wiring layer is an electrically conductive layer disposed on the surface of the glass core, and The insulating layer is disposed in the space between the electrically conductive layers and is a layer comprising a mixture of a polymer resin and insulating particles, and The above packaging substrate has an upper surface on which a semiconductor device is mounted and a lower surface opposite thereto, The insulating layer positioned on the upper part of the above glass core is an upper insulating layer, and A cover layer is further disposed on the upper portion of the upper insulating layer, and The insulating layer positioned at the bottom of the above glass core is a lower insulating layer, and A solder resist layer is further disposed below the above lower insulating layer, and The flexibility index FI is a value expressed by Equation 1 below, and The FI of the above cover layer has a value greater than the FI of the above solder resist layer, and A packaging substrate, wherein the difference between the FI of the cover layer and the FI of the solder resist layer is 3.6 or more and 4.2 or less; [Equation 1] FI = 10,000 Х (E' Х tan δ) / (H Х Er) In Equation 1 above, E' is the storage modulus (GPa), tan δ is the loss tangent, H is the hardness (GPa), and Er is the damping modulus (GPa).
  2. In paragraph 1, A packaging substrate having an FI of 7.5 or higher and 8.3 or lower for the above cover layer.
  3. In paragraph 1, A packaging substrate having an FI of the solder resist layer of 3.9 or higher and 4.6 or lower.
  4. In paragraph 1, A packaging substrate having a storage modulus (E') of 0.73 GPa or more and 0.85 GPa or less.
  5. In paragraph 1, A packaging substrate having a loss tangent (tan δ) of the above packaging substrate of 0.0080 or more and 0.0090 or less.
  6. In paragraph 1, A packaging substrate having a hardness (H) of the above cover layer of 0.55 GPa or more and 0.65 GPa or less.
  7. In paragraph 1, A packaging substrate having a hardness (H) of the solder resist layer of 0.82 GPa or more and 0.93 GPa or less.
  8. In paragraph 1, A packaging substrate having a damping modulus (Er) of the cover layer of the above, which is 13.5 GPa or more and 15.0 GPa or less.
  9. In paragraph 1, A packaging substrate having a damping modulus (Er) of the solder resist layer of 17.8 GPa or more and 19.6 GPa or less.

Description

Packaging Substrate The embodiment relates to a packaging substrate with improved thermal shock resistance, impact resistance, durability, reliability, etc., by controlling the difference in physical properties between the upper and lower parts of a glass core. In the production of electronic components, implementing circuits on a semiconductor wafer is called the front-end process (FE), and assembling the wafer into a state usable in an actual product is called the back-end process (BE), and the packaging process is included in the back-end process. The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. While semiconductor technology is evolving into various forms, such as sub-micron and nano-scale linewidths, over ten million cells, high-speed operation, and significant heat dissipation, the technology to perfectly package these technologies has not yet been sufficiently supported. Consequently, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections, rather than by the performance of the semiconductor technology itself. Ceramic or resin is used as the material for packaging substrates. In the case of ceramic substrates, it is difficult to mount high-performance, high-frequency semiconductor devices due to high resistance or dielectric constant. While resin substrates allow for the mounting of relatively high-performance, high-frequency semiconductor devices, there are limitations in reducing the wiring pitch. Recently, research is underway on applying glass substrates as packaging substrates for high-end applications. By forming through-holes in the glass substrate and applying conductive materials to these holes, the wiring length between the device and the motherboard can be shortened, and excellent electrical characteristics can be achieved. Related prior art includes Korean Publication No. 10-2020-0030430 and Korean Publication No. 10-2023-0145447. FIG. 1 is a packaging substrate on which a semiconductor device manufactured according to an embodiment is mounted. FIG. 2 is a conceptual diagram illustrating a cross-section viewed along the line A-A' of FIG. 1. FIG. 3 is a conceptual diagram illustrating a cross-section in which an upper insulating layer and a lower insulating layer are exposed on a packaging substrate manufactured according to an embodiment. FIG. 4 is a conceptual diagram illustrating a cross-section in which a cover layer and a solder resist layer are further arranged in FIG. 3. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Throughout the specification, similar parts are denoted by the same reference numerals. Throughout this specification, the term “combination thereof” included in the Markush-type expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-type expression, and means including one or more selected from the group consisting of said components. Throughout this specification, terms such as “first,” “second,” or “A,” “B” are used to distinguish identical terms from one another. Additionally, singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the “~” system may mean that the compound contains a compound corresponding to “~” or a derivative of “~”. In this specification, the meaning that B is located on A means that B is located in direct contact with A or that B is located on A with another layer located between them, and is not interpreted as being limited to B being located in contact with the surface of A. In this specification, the meaning of being connected to B on A means that A and B are directly connected or connected through other components between A and B, and unless otherwise specifically stated, it is not interpreted as being limited to a direct connection between A and B. In this specification, singular expressions are interpreted to include singular or plural forms as interpreted in context unless otherwise specified. In this specification, the shapes, relative sizes, angles, etc., of each component in the drawings are exemplary and may be exaggerated for illustrative purposes, and the rights are not interpreted as being limited to the drawings. In this specification, "A and B are adjacent" means that A and B are located in contact with each other, or that A and B are located close to each other even if they are not in contact. Unless otherwise specified, the expressi