Search

KR-20260064531-A - Packaging Substrate

KR20260064531AKR 20260064531 AKR20260064531 AKR 20260064531AKR-20260064531-A

Abstract

The packaging substrate of the embodiment is a packaging substrate comprising a glass core; a wiring layer; and an insulating layer; wherein the glass core is a plate-shaped glass having vias disposed therein, the wiring layer is an electrically conductive layer disposed on the surface of the glass core, the insulating layer is a layer disposed in the space between the electrically conductive layers and comprising a mixture of a polymer resin and insulating particles, and the packaging substrate has an upper surface on which an electronic device is mounted and a lower surface opposite thereto. A measurement point is a point on the surface of the packaging substrate, and 10 different measurement points are disposed on the surface. The measurement points have a distance from each other of at least 0.05 times the surface length. Er is an extreme surface equivalent modulus value (unit: GPa) measured by the nanoindentation method at the measurement point, the average of the extreme surface equivalent modulus values measured at the measurement points is Er_av, and the standard deviation of the extreme surface equivalent modulus values measured at the measurement points is Er_stdev. When considering the Er_av of the above packaging substrate as a whole, the ratio of the Er_stdev may be 7% or less. The packaging substrate of the embodiment can provide a packaging substrate with reduced overall stress by controlling the difference in extreme surface modulus according to the in-plane position within a certain range. In addition, it can provide a packaging substrate with improved reliability even when applying a glass core with brittle characteristics.

Inventors

  • 김성진
  • 김진철

Assignees

  • 앱솔릭스 인코포레이티드

Dates

Publication Date
20260507
Application Date
20251016
Priority Date
20241031

Claims (15)

  1. A packaging substrate comprising a glass core; a wiring layer; and an insulating layer, The above glass core is a plate-shaped glass with vias arranged therein, and The above wiring layer is an electrically conductive layer disposed on the surface of a glass core, and The insulating layer is disposed in the space between the electrically conductive layers and is a layer comprising a mixture of a polymer resin and insulating particles, and The above packaging substrate has an upper surface on which an electronic component is mounted and a lower surface opposite thereto, and The measurement point is a point on the surface of the packaging substrate, and Ten different measurement points are arranged on the surface, and The above measurement points have a distance of at least 0.05 times the surface length from each other, Er is the extreme surface equivalent modulus value (unit: GPa) measured by the nanoindentation method at the above measurement point, and The average of the polar surface converted modulus values measured at the above measurement points is Er_av, and The standard deviation of the polar surface converted modulus values measured at the above measurement points is Er_stdev, and The above measurement is performed at 27℃, and A packaging substrate in which the ratio of the above Er_stdev is 7% or less when the above Er_av is viewed as a whole.
  2. In paragraph 1, The above Er_av is 20 GPa or less, and The above Er_stdev is a packaging substrate having a thickness of 1 GPa or less.
  3. In paragraph 1, The insulating layer positioned on the upper part of the above glass core is an upper insulating layer, and A cover layer is further disposed on the upper portion of the above insulating layer, and The above cover layer is a polymer resin or an insulating inorganic layer, and The above surface is the side where the above cover layer is exposed, and A packaging substrate in which the largest value among the Er values of the above cover layer is 16 GPa or less.
  4. In paragraph 1, The insulating layer positioned at the bottom of the above glass core is a lower insulating layer, and A solder resist layer is further disposed below the above lower insulating layer, and The above surface is the surface where the above solder resist layer is exposed, and A packaging substrate in which the largest of the Er values of the above solder resist layer is 21 GPa.
  5. In paragraph 1, The average storage modulus (E') at 20℃ or higher and less than 30℃ is E'20, and The average storage modulus (E') at 140°C or higher and less than 150°C is E'140, and A packaging substrate in which E'20-E'140 of the above packaging substrate is 80 MPa or less.
  6. In paragraph 1, A packaging substrate having a loss modulus (E'') of 5 MPa or more at 30°C of the above packaging substrate.
  7. In paragraph 1, A packaging substrate having an extreme surface hardness (HIT) of less than 1 GPa measured at any point on the upper or lower surface of the packaging substrate.
  8. In paragraph 1, A packaging substrate having a contact compliance of 12 nm/mN or less.
  9. In paragraph 1, The insulating layer positioned on the upper part of the above glass core is an upper insulating layer, and A cover layer is further disposed on the upper portion of the above insulating layer, and The above cover layer is a polymer resin or an insulating inorganic layer, and The insulating layer positioned at the bottom of the above glass core is a lower insulating layer, and A solder resist layer is further disposed below the above lower insulating layer, and A packaging substrate in which the extreme surface hardness (HIT) of the cover layer and the extreme surface hardness (HIT) of the solder resist layer are both 0.3 GPa or higher.
  10. In Paragraph 9, A packaging substrate having a greater value for the extreme surface hardness (HIT) of the solder resist layer than the extreme surface hardness (HIT) of the cover layer.
  11. In Paragraph 9, A packaging substrate having an extreme surface hardness (HIT) of the solder resist layer of 0.8 GPa or higher.
  12. In paragraph 1, The measurement point is a point on the surface of the packaging substrate, and Ten different measurement points are arranged on the surface, and The above measurement points have a distance of at least 0.05 times the diameter or diagonal length of the packaging substrate, and HIT is the extreme surface hardness (unit: GPa) measured by the nanoindentation method at the above measurement point, and The standard deviation of the extreme surface hardness values measured at the above measurement points is HIT_stdev, and The above HIT_stdev is a packaging substrate having a pa of 0.1 GPa or less.
  13. In paragraph 1, A packaging substrate in which the difference between the largest and smallest Er values among the individual measurement points of the packaging substrate is 4 GPa or less.
  14. In paragraph 1, The above surface is the side where the insulation layer is exposed, and A packaging substrate in which the largest value among the Er values of the insulating layer is 22 GPa or less.
  15. In paragraph 1, A packaging substrate having a tan delta value of 0.009 or less at 30℃.

Description

Packaging Substrate An embodiment relates to a packaging substrate in which extreme surface modulus, etc. is controlled. Additionally, an embodiment relates to a packaging substrate in which loss modulus, hardness, etc. are controlled. In the production of electronic components, implementing circuits on a semiconductor wafer is called the front-end process (FE), and assembling the wafer into a state usable in an actual product is called the back-end process (BE), and the packaging process is included in the back-end process. The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. While semiconductor technology is evolving into various forms, such as sub-micron and nano-scale linewidths, over ten million cells, high-speed operation, and significant heat dissipation, the technology to perfectly package these technologies has not yet been sufficiently supported. Consequently, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections, rather than by the performance of the semiconductor technology itself. Ceramic or resin is used as the material for packaging substrates. In the case of ceramic substrates, it is difficult to mount high-performance, high-frequency semiconductor devices due to high resistance or dielectric constant. While resin substrates allow for the mounting of relatively high-performance, high-frequency semiconductor devices, there are limitations in reducing the wiring pitch. Recently, research is underway on applying glass substrates as packaging substrates for high-end applications. By forming through-holes in the glass substrate and applying conductive materials to these holes, the wiring length between the device and the motherboard can be shortened, and excellent electrical characteristics can be achieved. Related prior art includes Korean Publication No. 10-2020-0030430 and Korean Publication No. 10-2023-0145447. Hereinafter, embodiments are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Throughout the specification, similar parts are denoted by the same reference numerals. Throughout this specification, the term “combination thereof” included in the Markush-type expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-type expression, and means including one or more selected from the group consisting of said components. Throughout this specification, terms such as “first,” “second,” or “A,” “B” are used to distinguish identical terms from one another. Additionally, singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the “~” system may mean that the compound contains a compound corresponding to “~” or a derivative of “~”. In this specification, the meaning that B is located on A means that B is located in direct contact with A or that B is located on A with another layer located between them, and is not interpreted as being limited to B being located in contact with the surface of A. In this specification, the meaning of being connected to B on A means that A and B are directly connected or connected through other components between A and B, and unless otherwise specifically stated, it is not interpreted as being limited to a direct connection between A and B. In this specification, singular expressions are interpreted to include singular or plural forms as interpreted in context unless otherwise specified. In this specification, the shapes, relative sizes, angles, etc., of each component in the drawings are exemplary and may be exaggerated for illustrative purposes, and the rights are not interpreted as being limited to the drawings. In this specification, "A and B are adjacent" means that A and B are located in contact with each other, or that A and B are located close to each other even if they are not in contact. Unless otherwise specified, the expression "A and B are adjacent" in this specification is not interpreted as being limited to A and B being in contact with each other. Unless otherwise specified in this specification, the physical property values of each component within the packaging substrate are interpreted as being measured at room temperature. Room temperature is 20°C to 25°C. Depending on the design, wiring layers, insulating layers, cover layers, solder resist layers, etc., may be arranged in various forms in multiple layers on the upper or lower portions of the packaging substrate, respectively. Additionally, the height of these wiring