KR-20260064535-A - Method for manufacturing shielded gate trench MOSFET

Abstract

The present invention relates to a shielded gate trench (SGT) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for manufacturing the same. According to the present invention, in order to solve the problems of conventional SGT MOSFET manufacturing methods, which had limitations such as increased manufacturing costs due to the use of multiple masks in the manufacturing process and increased process errors due to the complexity of the overall manufacturing process leading to a decrease in yield, a method for manufacturing an SGT MOSFET is provided that simplifies the overall manufacturing process and reduces costs by reducing the number of masks used in manufacturing the SGT MOSFET, while simultaneously improving the precision of the process by applying a self-alignment technique.

Inventors

• 정영서

Assignees

• 주식회사 티디에스

Dates

Publication Date

20260507

Application Date

20251017

Priority Date

20241030

Claims (9)

1. In a method for manufacturing a shielded gate trench (SGT) metal-oxide-semiconductor field-effect transistor (MOSFET), Preparation stage for preparing the substrate; A trench formation step of forming a trench in the substrate according to a predetermined setting; A shield forming step of forming a shield inside the trench according to a predetermined setting; A gate formation step of forming a gate region using ion implantation according to a predetermined setting; A source formation step of forming a source region using ion implantation according to a predetermined setting; and A method for manufacturing an SGT MOSFET characterized by being configured to perform a process including a pattern formation step for manufacturing an SGT MOSFET by forming a pattern according to a predetermined setting.
2. In Article 1, The above trench formation step is, An epitaxial step of forming an epitaxial layer by applying impurities to the substrate according to a predetermined setting; and A method for manufacturing an SGT MOSFET characterized by comprising a shield gate trench formation step of forming a shield gate trench by performing a photolithography process using a mask and etching on a substrate on which an epitaxial layer is formed according to a predetermined setting.
3. In Article 1, The above shield formation step is, A shield gate oxide formation step of forming a shield gate oxide film (Field Oxide) inside the trench according to a predetermined setting; A shield polysilicon deposition step of depositing shield polysilicon inside the shield gate oxide film according to a predetermined setting; A shield formation step of forming a shield at the bottom of a trench by etching the shield polysilicon by performing an etch back using a mask according to a predetermined setting; and A method for manufacturing an SGT MOSFET characterized by comprising an IPD (Inter-Poly Dielectric) formation step of forming an IPD layer by applying a dielectric material according to a predetermined setting.
4. In Article 1, The above gate formation step is, A body region formation step of forming a P-type body region (P-body) for forming a channel in the trench wall without using a separate mask by using angle-adjusted ion implantation (Angled Implant) according to a predetermined setting; A gate oxide formation step of forming a gate oxide on the trench wall according to a predetermined setting; and A method for manufacturing an SGT MOSFET, characterized by comprising a gate polysilicon formation step of depositing gate polysilicon on the trench wall according to a predetermined setting and performing an etch-back to remove a portion of the gate polysilicon.
5. In Article 1, The above source formation step is, A body region formation step of forming a P-type body region (P-body) using blank implantation according to a predetermined setting; NSD formation step of forming an N+ source region (NSD) without using a mask by using angled implant or blank implant according to a predetermined setting; A contact hole formation step of depositing a dielectric layer on the top surface according to a predetermined setting and then etching a contact hole to a certain depth through a contact mask and photo process; and A method for manufacturing an SGT MOSFET characterized by comprising a PSD formation step of forming a P+ region (PSD) in a P-body region without using a mask by performing p+ ion implantation in a contact hole according to a predetermined setting.
6. In Paragraph 5, The above contact hole forming step is, A method for manufacturing an SGT MOSFET characterized by being configured to etch the contact hole to a depth corresponding to the lower part of the N+ source region (NSD).
7. In Article 1, The above pattern formation step is, A deposition step for performing contact-fill and metal deposition according to a predetermined setting; and A method for manufacturing an SGT MOSFET characterized by comprising a patterning step that performs metal patterning according to a predetermined setting.
8. A semiconductor device characterized by being manufactured using the SGT MOSFET manufacturing method described in any one of claims 1 to 7.
9. An electronic device characterized by comprising a semiconductor device manufactured using the SGT MOSFET manufacturing method described in any one of claims 1 to 7.

Description

Method for manufacturing shielded gate trench MOSFET The present invention relates to a shielded gate trench (SGT) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for manufacturing the same. More specifically, the invention relates to a method for manufacturing an SGT MOSFET configured to reduce the number of masks used in manufacturing the SGT MOSFET, thereby enabling a reduction in overall manufacturing costs and an improvement in yield. This is done to solve the problems of conventional SGT MOSFET manufacturing methods, which, despite having high integration density and excellent electrical characteristics compared to conventional planar MOSFETs, had limitations such as increased manufacturing costs due to the requirement of using a large number of photolithography masks, and yield reduction problems caused by mis-alignment due to the complexity of the overall manufacturing process. Furthermore, in order to solve the problems of conventional SGT MOSFET manufacturing methods, which had limitations such as increased manufacturing costs and increased process errors leading to reduced yield due to the complexity of the overall manufacturing process resulting from the use of multiple masks as described above, the present invention is configured to perform a process that improves process precision by applying an angled implant method to a trench wall during the SGT MOSFET manufacturing process to form a p-body without a separate p-body mask, forming a source terminal without a separate n+ mask through a blank implant process, directly forming a p+ component in a contact hole using a contact mask, and applying a self-alignment technique. By doing so, the present invention reduces the number of mask steps required during SGT MOSFET manufacturing, thereby simplifying the overall manufacturing process and reducing costs, and consequently improving process precision to increase yield. This relates to a method for manufacturing an SGT MOSFET. Recently, as semiconductor technology advances, there is an increasing demand for miniaturization, high integration, and high performance of various electronic products. Consequently, shielded gate trench (SGT) MOSFETs, which possess superior characteristics compared to conventional metal-oxide-semiconductor field-effect transistors (MOSFETs), are being widely used. These SGT MOSFETs are primarily used in power semiconductor devices that provide efficient power control and low conduction losses in high-power applications, thanks to their advantages of higher integration density and superior electrical characteristics compared to conventional planar MOSFETs. In addition, as presented in, for example, "Trench Power MOSFET and Method of Manufacturing the Same" in Korean Registered Patent Publication No. 10-2444384 and "4H-SiC Based Trench Gate Transistor with High Breakdown Voltage" in Korean Published Patent Publication No. 10-2532142, various technical contents regarding SGT MOSFETs and methods of manufacturing the same have been presented in the past, but the contents of the prior art as described above had the following limitations. More specifically, as mentioned above, generally, SGT MOSFETs have the advantage of high integration density and excellent electrical characteristics compared to conventional planar MOSFETs, but they have limitations such as increased manufacturing costs due to the use of multiple photolithography masks in the manufacturing process, and a problem of reduced yield caused by mis-alignment due to the complexity of the manufacturing process. In other words, the existing SGT MOSFET manufacturing method uses, for example, a method of forming the p-body and source/drain using multiple masks, but this method increases the overall process cost and process complexity as a result of using many masks, and there was a problem in that alignment errors occurred due to such a complex process, leading to a decrease in overall yield. Here, in order to solve these problems, it is required to reduce the number of masks used in the manufacturing process and reduce alignment errors to improve process precision, but the contents of the SGT MOSFET and the manufacturing method of the prior art as described above have limitations in that no method for reducing the number of masks used and improving process precision in this way is presented. Therefore, in order to overcome the limitations of the conventional SGT MOSFET manufacturing methods described above, it is desirable to present a new SGT MOSFET manufacturing method configured to simplify the overall manufacturing process and reduce costs by reducing the mask steps required during SGT MOSFET manufacturing, for example by introducing self-alignment and a new ion implantation method, and thereby improve process precision and increase yield; however, a device or method that satisfies all such requirements has not yet been presented. FIG. 1 is a diagram schematically showing the overall configuratio