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KR-20260064565-A - SUBSTRATE AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME

KR20260064565AKR 20260064565 AKR20260064565 AKR 20260064565AKR-20260064565-A

Abstract

A substrate according to an embodiment includes a glass core. The glass core includes through-vias that penetrate the glass core in the thickness direction. The diameter of the through-vias is 50 μm to 100 μm. The sum of the sulfur content (atomic%) and nitrogen content (atomic%) of the glass core is 0.2 atomic% to 8 atomic%. In this case, it is possible to provide a substrate (100) that has stable durability and electrical reliability even in a high-humidity environment, and more stably implements electrical connections penetrating the glass core.

Inventors

  • 김성진
  • 김진철

Assignees

  • 앱솔릭스 인코포레이티드

Dates

Publication Date
20260507
Application Date
20251024
Priority Date
20241031

Claims (15)

  1. Includes a glass core, The above glass core includes a through-via penetrating the glass core in the thickness direction, and The diameter of the above-mentioned through via is 50㎛ to 100㎛, and A substrate in which the sum of the sulfur content (atomic%) and nitrogen content (atomic%) of the above glass core is 0.2 atomic% to 8 atomic%.
  2. In paragraph 1, The above glass core is a substrate containing 0.1 atomic% to 3 atomic% of sulfur.
  3. In paragraph 1, The above glass core is a substrate containing 0.1 atomic% to 5 atomic% of nitrogen.
  4. In paragraph 1, The above glass core includes an upper surface and a lower surface facing the upper surface, and The above through-via has a diameter that varies in the thickness direction of the substrate, and A substrate comprising a through-via including a first opening in contact with the upper surface of the glass core, a second opening in contact with the lower surface of the glass core, and a minimum inner diameter portion connecting the first opening and the second opening and having the smallest diameter.
  5. In paragraph 4, The above-mentioned through via includes an internal space and a via inner diameter surface surrounding the internal space, and A substrate, wherein when observed in a cross-section in the thickness direction of the glass core, the angle formed by the inner diameter surface of the via connecting the minimum inner diameter portion and the first opening and the vertical line to the upper surface of the glass core is 0.1° to 8°.
  6. In paragraph 1, The above-mentioned through via includes an internal space and a via inner diameter surface surrounding the internal space, and It includes an electrically conductive layer formed on the inner diameter surface of the above-mentioned via, and The above electrically conductive layer comprises a seed layer and a conductive layer disposed on the seed layer, and A substrate having a seed layer thickness of 50 nm to 500 nm.
  7. In paragraph 1, It further includes an insulating layer disposed on the above glass core, and The above insulating layer comprises an insulating resin, and A substrate having an Ih value, which is the hydrophilicity index of the insulating layer in Formula 1 below, of 7 to 12; [Equation 1] In the above Equation 1, The above Rcc value is the ratio of the abundance of carbon-carbon bonds to the total carbon-element bonds, and The above Rco value is the ratio of the abundance of carbon-oxygen bonds to the total carbon-element bonds.
  8. In Paragraph 7, The above insulating layer further includes a filler, and The above filler contains silica, and A substrate having an Irw value, which is the moisture resistance index of the insulating layer in Equation 2 below, of 0.03% to 0.1%; Irw = Rso(%) + Rsc(%) In the above Equation 2, The above Rso value is the abundance (%) of single silicon-oxygen bonds relative to total silicon-atomic bonds, and The above Rsc value is the ratio (%) of the abundance of single silicon-carbon bonds to the total silicon-element bonds.
  9. In Paragraph 7, A substrate in which the abundance ratio of carbon-carbon double bonds relative to the total carbon-atomic bonds of the insulating layer is 12% to 17%.
  10. In Paragraph 7, A substrate having a water absorption rate of 0.1% or less measured after immersion in water at 23℃ for 24 hours.
  11. In Paragraph 7, A substrate having a tensile strength of 60 MPa or higher.
  12. In paragraph 8, The above filler further comprises a metal oxide, and The above filler comprises 30% to 70% by weight of the metal oxide, a substrate.
  13. In Paragraph 7, The above insulating resin includes an epoxy resin, and The above epoxy resin comprises a first residue derived from a bisphenol-type epoxy resin and a second residue derived from a novolak-type epoxy resin, forming a substrate.
  14. In paragraph 1, A substrate having a semiconductor package application.
  15. It includes a glass core and an insulating layer disposed on the glass core, and The above insulating layer comprises an insulating resin, and A substrate having an Ih value, which is the hydrophilicity index of the insulating layer in Formula 1 below, of 7 to 12; [Equation 1] In the above Equation 1, The above Rcc value is the ratio of the abundance of carbon-carbon bonds to the total carbon-element bonds, and The above Rco value is the ratio of the abundance of carbon-oxygen bonds to the total carbon-element bonds.

Description

Substrate and semiconductor package comprising the same An embodiment relates to a substrate and a semiconductor package including the same. In the production of electronic components, implementing circuits on a semiconductor wafer is called the front-end process (FE), and assembling the wafer into a state usable in an actual product is called the back-end process (BE), and the packaging process is included in the back-end process. The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. While semiconductor technology is evolving into various forms, such as sub-micron and nano-scale linewidths, over ten million cells, high-speed operation, and significant heat dissipation, the technology to perfectly package these technologies has not yet been sufficiently supported. Consequently, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections, rather than by the performance of the semiconductor technology itself. Ceramic or resin is used as the material for the substrate (100). In the case of a ceramic substrate, it is difficult to mount high-performance high-frequency semiconductor devices because the resistance value is high or the dielectric constant is high. In the case of a resin substrate, it is possible to mount relatively high-performance high-frequency semiconductor devices, but there is a limit to reducing the pitch of the wiring. Recently, research is being conducted on using silicon or glass as a high-end substrate (100). By forming through holes in the silicon or glass substrate and applying a conductive material to these through holes, the wiring length between the device and the motherboard can be shortened and excellent electrical characteristics can be obtained. FIG. 1a is a cross-sectional view illustrating a substrate according to one embodiment of the embodiment. FIG. 1b is an enlarged view of A shown in FIG. 1a. FIG. 2 is a cross-sectional view illustrating a substrate according to another embodiment of the embodiment. FIG. 3 is a cross-sectional view illustrating a substrate according to another embodiment of the embodiment. FIG. 4 is a cross-sectional view illustrating a substrate (100) according to another embodiment of the embodiment. FIG. 5 is a cross-sectional view illustrating a substrate (100) according to another embodiment of the embodiment. Hereinafter, embodiments are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Throughout the specification, similar parts are denoted by the same reference numerals. Throughout this specification, the term “combination thereof” included in the Markush-type expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-type expression, and means including one or more selected from the group consisting of said components. Throughout this specification, terms such as “first,” “second,” or “A,” “B” are used to distinguish identical terms from one another. Additionally, singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the “~” system may mean that the compound contains a compound corresponding to “~” or a derivative of “~”. In this specification, the meaning that B is located on A means that B is located in direct contact with A or that B is located on A with another layer located between them, and is not interpreted as being limited to B being located in contact with the surface of A. In this specification, the meaning of being connected to B on A means that A and B are directly connected or connected through other components between A and B, and unless otherwise specifically stated, it is not interpreted as being limited to a direct connection between A and B. In this specification, singular expressions are interpreted to include singular or plural forms as interpreted in context unless otherwise specified. In this specification, the shapes, relative sizes, angles, etc., of each component in the drawings are exemplary and may be exaggerated for illustrative purposes, and the rights are not interpreted as being limited to the drawings. In this specification, "A and B are adjacent" means that A and B are located in contact with each other, or that A and B are located close to each other even if they are not in contact. Unless otherwise specified, the expression "A and B are adjacent" in this specification is not interpreted as being limited to A and B being in contact with each other. In this specification, the term "fine lin