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KR-20260064623-A - Trench MOSFET device including shielding layer and manufacturing method thereof

KR20260064623AKR 20260064623 AKR20260064623 AKR 20260064623AKR-20260064623-A

Abstract

The present invention relates to a trench-type metal oxide silicon field effect transistor (MOSFET). According to the present invention, a shielding layer (Shielding P-Layer) having the same conductivity type as the body layer is formed at the bottom of the trench, and a current spreading layer (CSL) is formed in the drift region between the shielding layers to optimize the electric field and current distribution. This configuration allows for effective reduction of Cdg without increasing process complexity, alleviation of electric field concentration at the bottom of the trench to prevent oxide breakdown and breakdown voltage drop, suppression of the increase in RDS(on) caused by the JFET effect that may occur upon the introduction of the shielding layer, and optimization of the electric field distribution and current path through the combination of the shielding layer and the CSL to improve both switching speed and energy efficiency. A trench MOSFET including a shielding layer and a method for manufacturing the same are provided.

Inventors

  • 정영서

Assignees

  • 주식회사 티디에스

Dates

Publication Date
20260507
Application Date
20251030
Priority Date
20241031

Claims (10)

  1. In a trench MOSFET (Metal Oxide Silicon Field Effect Transistor) including a shielding layer, Substrate; A drift layer formed on the substrate according to a predetermined setting; A plurality of trenches formed in the drift layer according to a predetermined setting; A shielding layer formed at the bottom of each trench according to a predetermined setting to have the same conductivity type as the body area; A current spreading layer (CSL) formed between each shielding layer according to a predetermined setting to have the same conductivity type as the drift layer; A field oxide layer (FOX) formed on the upper part of the shielding layer according to a predetermined setting; A gate oxide (GOX) formed on the upper part of the trench according to a predetermined setting; A gate electrode (Gate Poly) formed of polysilicon or a metal gate on the upper part of the trench according to a predetermined setting; and A trench MOSFET including a shielding layer characterized by being configured to include an inter-layer dielectric (ILD), a contact region, a source region (PSD, NSD), a body region (P-body), and an electrode (Gate, Source Body) formed on the upper surface of the trench MOSFET according to a predetermined setting.
  2. In Article 1, The above substrate is, A trench MOSFET including a shielding layer, characterized by being configured using a semiconductor substrate formed using at least one of a material including silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaOx) according to a predetermined setting.
  3. In Article 1, The above shielding layer is, A trench MOSFET including a shielding layer, characterized by being configured to be formed by implanting boron (B) ions into the bottom of the trench using ion implantation according to a predetermined setting at a doping concentration in the range of 1× 10¹⁵ to 1× 10¹⁸ cm⁻³ .
  4. In Article 1, The above shielding layer is, A trench MOSFET including a shielding layer characterized by forming a Deep P-Well (PW) layer in a part of a body region according to a predetermined setting so as to be electrically connected to the body region.
  5. In Article 1, The above shielding layer is, A trench MOSFET including a shielding layer characterized by being configured such that a Schottky contact is additionally formed in some areas according to a predetermined setting.
  6. In Article 1, The above current diffusion layer (CSL) is, A trench MOSFET including a shielding layer, characterized by being configured to be formed by implanting phosphorus (P) or arsenic (As) ions into the drift layer between the shielding layers using ion implantation according to a predetermined setting at a doping concentration in the range of 1× 10¹⁵ to 1× 10¹⁹ cm⁻³ .
  7. In a method for manufacturing a trench MOSFET including a shielding layer, A step of preparing a substrate according to a predetermined setting; A step of forming a drift region (N-Drift) by forming an epitaxial layer by applying impurities to the substrate according to a predetermined setting, and then forming a trench through a photolithography process using a mask and etching; A step of forming a shielding layer (P-Shield) by injecting impurities of the same conductivity type as the body region into the bottom of the trench according to a predetermined setting; A step of forming a current diffusion layer (CSL) by injecting impurities of the same conductivity type as the drift region between the shielding layers according to a predetermined setting; A step of forming a field oxide layer (FOX) at the bottom of the trench according to a predetermined setting; A step of electrically connecting the shielding layers by forming a Deep P-well (Deep PW) between the shielding layers according to a predetermined setting; and A method for manufacturing a trench MOSFET including a shielding layer, characterized by comprising the step of forming a gate oxide film (GOX) and a gate electrode (Gate Poly) on the upper surface of the trench according to a predetermined setting, and forming an interlayer insulating film (ILD), a contact region (Contact), a source region (PSD, NSD), a body region (P-body), and an electrode (Gate, Source Body) respectively on the upper surface of the trench MOSFET to complete the trench MOSFET.
  8. In Article 7, The step of forming the shielding layer (P-Shield) described above is: According to a predetermined setting, boron (B) ions are injected into the bottom of the trench using ion implantation at a doping concentration in the range of 1× 10¹⁵ to 1× 10¹⁸ cm⁻³ to form the shielding layer, and A method for manufacturing a trench MOSFET including a shielding layer, characterized by forming a Deep P-Well (PW) layer in a part of the body region according to a predetermined setting to electrically connect the shielding layer.
  9. In Article 7, The step of forming the above current diffusion layer (CSL) is, A method for manufacturing a trench MOSFET including a shielding layer, characterized by being configured to form the current diffusion layer (CSL) by implanting phosphorus (P) or arsenic (As) ions into the drift layer between the shielding layers using ion implantation according to a predetermined setting at a doping concentration in the range of 1× 10¹⁵ to 1× 10¹⁹ cm⁻³ .
  10. In Article 7, The above manufacturing method is, A method for manufacturing a trench MOSFET including a shielding layer, characterized by configuring to form P+ (PSD) through blank boron (B) ion implantation after etching a contact hole to pass through the dielectric layer and the lower N+ layer.

Description

Trench MOSFET including shielding layer and manufacturing method thereof The present invention relates to a trench-type metal oxide silicon field effect transistor (MOSFET), and more specifically, to a trench MOSFET including a shielding layer configured to effectively reduce the drain-gate capacitance (Cdg) in a conventional trench-gate type power MOSFET and a method for manufacturing the same, in order to solve the problems of the conventional trench gate type power MOSFET structure and manufacturing method, which generally had limitations in that the drain-gate capacitance (Cdg) increased as the gate-drain overlap region increased due to the gate electrode being formed deep in the drift region, thereby reducing the switching speed and increasing switching losses and lowering overall efficiency. Furthermore, to resolve the problems of the conventional shielded gate trench (SGT) structure and its manufacturing methods—which faced limitations in commercialization due to increased ON resistance (RDS(on)) between drain and source and decreased breakdown voltage (BVdss) caused by the Junction Field Effect Transistor (JFET) effect—by configuring the addition of a gate shield layer including an insulating layer (Field Oxide) at the bottom of the trench to resolve the issues of the existing trench gate type power MOSFET described above, thereby complicating the overall manufacturing process and increasing manufacturing costs, the present invention is configured to form a shielding P-layer having the same conductivity type as the body layer at the bottom of the trench and to form a current spreading layer (CSL) in the drift region between the shielding layers to optimize the electric field and current distribution, thereby addressing the existing The present invention relates to a trench MOSFET including a shielding layer configured to effectively reduce drain-gate capacitance (Cdg) and increase switching speed in a trench gate type power MOSFET, while simultaneously mitigating electric field concentration at the bottom of the trench to reduce switching losses and oxide film degradation, thereby improving power conversion efficiency, and a method for manufacturing the same. Conventionally, trench-type MOSFETs are widely used in various power conversion circuits as high-efficiency power switching devices due to their high cell density and low conduction resistance per unit area (RDS(on)). However, conventional trench gate structures have limitations in that the gate electrode is formed deep within the drift region, which increases the overlap region between the gate and drain, and consequently increases the drain-gate capacitance (Cdg), i.e., Miller capacitance, which reduces the switching speed and increases switching losses, thereby lowering the overall efficiency. To this end, a shielded gate trench (SGT) structure has been proposed in the past, which includes a gate shield layer containing an insulating layer (Field Oxide) at the bottom of the trench. However, this structure had limitations in commercialization due to problems such as increased process complexity, increased manufacturing costs, increased RDS(on) and decreased breakdown voltage (BVdss) caused by the JFET effect. In addition, a method of forming a P-type shielding layer (p-shield) at the bottom of the trench has been proposed in the past; however, while this is effective in mitigating electric field concentration, it has limitations in that its Cdg reduction effect is limited and it fails to provide sufficient performance improvement in high-frequency switching environments. Therefore, in order to solve the problems of the conventional trench MOSFET devices and manufacturing methods described above, a new configuration of trench MOSFET and a manufacturing method thereof are required to improve energy efficiency by effectively reducing drain-gate capacitance (Cdg) to increase switching speed, while simultaneously minimizing the reduction of breakdown voltage (BVdss) and RDS(on) to reduce switching losses; however, a device or method that satisfies all such requirements has not yet been presented. FIG. 1 is a cross-sectional view schematically showing the overall configuration of a trench MOSFET including a shielding layer according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing a configuration in which a shielding layer is electrically connected through a deep P-well in a trench MOSFET including a shielding layer according to another embodiment of the present invention shown in FIG. 1, in which the shielding layer is partially formed. FIG. 3 is a flowchart schematically showing the overall configuration of a trench MOSFET manufacturing method including a shielding layer according to an embodiment of the present invention. Figure 4 is a graph showing the results of comparing the Cgd-Vds characteristics of a trench MOSFET including a shielding layer according to an embodiment of the present invention and a trench MO