KR-20260064666-A - High-Bandwidth Memory with Bridge-Integrated Logic Die and Package Therefor

Abstract

The present invention provides a heterogeneous integrated package in which a high bandwidth memory and a process chip using the same are mounted, comprising: a package substrate; a logic die located on top of the package substrate and including a co-physical layer for the high bandwidth memory; a process chip located on top of the logic die and electrically connected via the logic die, including a physical layer corresponding to the co-physical layer; and a memory package composed of two or more memory dies, wherein the logic die includes high-speed interconnects that connect the physical layer and the co-physical layer without through-electrodes and have a length of 4 millimeters or less.

Inventors

• 이종주

Assignees

• 이종주

Dates

Publication Date

20260507

Application Date

20260407

Priority Date

20231227

Claims (13)

1. package substrate and; A logic die located on the upper part of the above package substrate and including a companion physical layer for high bandwidth memory; A process chip comprising a physical layer corresponding to the companion physical layer, which is located above the logic die and is electrically connected via the logic die, and a memory package composed of two or more memory dies; The above logic die is a heterogeneous integrated package that connects the physical layer and the companion physical layer without through-electrodes.
2. In paragraph 1, The above logic die is, A first interconnect that electrically connects the above physical layer and the above companion physical layer, and It further includes a second interconnect that electrically connects the aforementioned companion physical layer and the aforementioned memory package, and A heterogeneous integrated package in which the speed of a data signal transmitted through the first interconnect is faster than the speed of a data signal transmitted through the second interconnect.
3. In paragraph 2, A heterogeneous integrated package further comprising a repeater circuit connected to the second interconnect on the logic die.
4. In paragraph 2, A heterogeneous integrated package in which the second interconnect has N times more physical numbers (N is a number greater than or equal to 2) than the first interconnect, and the speed of the transmitted data signal is set to be 1/N times slower.
5. In any one of paragraphs 2 through 4, The above second interconnect is a heterogeneous integrated package configured such that the interconnect going to the memory package from the above companion physical layer and the interconnect coming in the opposite direction are separated.
6. In paragraph 2, A heterogeneous integrated package in which the length of the first interconnect is 4 millimeters or less, and the length of the second interconnect is set to be longer than the length of the first interconnect.
7. In paragraph 1, The above memory dies are a heterogeneous integrated package consisting of DRAM dies connected and stacked using through-electrodes.
8. In paragraph 1, The above logic die may be embedded inside the package substrate or mounted on the surface or inside a hole of the package substrate, forming a heterogeneous integrated package.
9. In paragraph 1, A heterogeneous integrated package having a cooler for heat dissipation formed on the upper part of the process chip and the memory package.
10. In Paragraph 9, A heterogeneous integrated package that blocks heat transfer from the process chip to the memory package by forming a heat-blocking structure between the process chip and the memory package.
11. In paragraph 1, A plurality of bondings are formed on the lower part of the above logic die and through electrodes are formed inside to connect them, and One side of the plurality of bondings and through-electrodes provides power and signals for separate purposes to the memory package, the process chip, and the physical layer, and The other side of the plurality of bondings and through-electrodes is a heterogeneous integrated package that provides power and signals for separate purposes to circuits inside the logic die.
12. In paragraph 1, A plurality of substrate wirings formed on the above package substrate, and A heterogeneous integrated package in which some power and signals for a separate purpose are provided directly through the plurality of substrate wirings without passing through the logic die.
13. package substrate and; A logic die located on the upper part of the above package substrate and including a companion physical layer for high bandwidth memory; A process chip comprising a physical layer corresponding to the companion physical layer, which is located above the logic die and electrically connected via the logic die, and a memory package composed of two or more memory dies; The logic die is located on the package substrate independently of the memory dies to provide vertical clearance so that more memory dies can be stacked, and includes a companion physical layer to serve as a bridge to bridge with the physical layer of the process chip. A heterogeneous integrated package in which the above-mentioned co-physical layer is formed at a free position on the logic die, and the connection between the physical layer and the co-physical layer is formed by an interconnect of 4 millimeters or less formed on the logic die without passing through a through-electrode.

Description

High-Bandwidth Memory with Bridge-Integrated Logic Die and Package Therefor The present invention relates to a High-Bandwidth Memory (hereinafter referred to as 'HBM') and a Processor, etc., integrated into a single package in a 2.5-dimensional (2.5D) or 3-dimensional (3D) heterogeneously integrated package, and structures of a heterogeneously integrated package employing the same. With the advent of the data-centric era, the demand for high-performance and high-capacity memory solutions is increasing, and HBM is establishing itself as a core technology leading this technological trend. With the advantages of high bandwidth and low power consumption, HBM can significantly improve the speed and efficiency of data processing in fields such as artificial intelligence, big data analysis, autonomous vehicles, and scientific research, where large-scale data processing and high-performance computing are essential. This HBM is able to provide large bandwidth by having thousands of data input/output pins (typically bumps formed for bonding), up to 1,024 for HBM3E and 2,048 for HBM4. However, in order to physically and electrically interconnect so many high-speed input/output pins for communication with the process chip, fine wiring (Interconnect; hereinafter referred to as 'Interconnect') is required, so 2.5-dimensional or 3-dimensional heterogeneous integrated package technology employing silicon-based interposers or bridges is commonly used for this purpose. Heterogeneous integrated packages (100a, 100b) employing HBM according to the prior art additionally use an intermediary substrate, such as a silicon interposer (120) or a silicon bridge (130), to implement high-speed interconnects (126, 136) that electrically interconnect the data input/output pins of the process chip (140) and the HBM package (150), as shown in the example illustrated in FIG. 1a and 1b. The prior art HBM package (150) comprises memory dies for HBM (Memory Dies; 151a to 151d) stacked in multiple layers; It is composed of a logic die (160) which can be called an HBM controller, located below the memory dies (151a to 151d), and may include circuits and wiring related to the management of the memory dies (151a to 151d), and includes at least communication functions to the outside of the memory dies (151a to 151d) and the HBM package (150). Currently, DRAM is used as the memory die, and they are all physically/electrically connected by including through-silicon vias (152a to 152d, 162) and bondings (153a to 153d). Although the present invention is illustrated as a case where four HBM memory dies (151a to 151d) are applied, it is obvious that the same can be applied even when more (e.g., 16) HBM memory dies are stacked. Communication between the process chip (140) and the HBM package (150) is performed by physical layers (commonly referred to as PHYs) that handle physical aspects such as signal transmission, reception, and modulation. Referring to FIGS. 1a and 1b, signal/data input/output is performed by the physical layer (145) for HBM of the process chip (140) and the companion physical layer (165) within the logic die (160) for HBM constituting the HBM package (150). These are physically/electrically connected to each other by bondings (147, 167) between the two chips (140, 160) and high-speed interconnects (126, 136) within the silicon interposer (120) or bridge (130). The number of wires including through electrodes (152a to 152d) and bondings (153a to 153d) connecting the co-physical layer (165) of the logic die for HBM and the memory dies (151a to 151d) for HBM stacked on the logic die is a multiple of the number of high-speed interconnects (126, 136) on the interposer (120) or bridge (130). This is because, by using a serializer/deserializer circuit in the co-physical layer (165) of the logic die for HBM, the signal transmission speed between them can be slowed down by an inverse multiple to maintain the same bandwidth relative to the multiple that increases the number of connections between the co-physical layer (165) and each of the memory dies (151a to 151d). By doing this, the burden of driving each memory die (151a to 151d) at high speed is reduced, while the signal integrity problem caused by the increased load (typically Capacitive Loading) resulting from connecting multiple HBM memory dies (151a to 151d) together for high capacity can also be mitigated. For example, assuming that high-speed interconnects (126, 136) within the interposer (120) or bridge (130), that is, the physical layer (145) for HBM of the process chip and the co-physical layer (165) of the logic die for HBM are interconnected with 1,024 high-speed interconnects (126, 136) for data input/output and operate at a speed of 6.4 gigabits per second (Gbps), and assuming that an HBM package (150) with 8 stacked HBM memory dies is used, the number of wires for data input/output between the co-physical layer (165) of the logic die for HBM and the HBM memory dies (151a to 1