KR-20260064676-A - SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR

Abstract

A semiconductor device comprises: a lower structure including a lower source/drain pattern; a lower embedded pattern on the lower structure; and an upper structure on the lower embedded pattern, wherein the upper structure comprises upper channel stacks spaced apart from each other in a first direction, each of the upper channel stacks including upper semiconductor patterns stacked and spaced apart from each other in a second direction perpendicular to the first direction; an upper source/drain pattern between two adjacent upper channel stacks; and upper inner electrodes interposed between adjacent upper semiconductor patterns. and upper inner spacers interposed between each of the upper inner electrodes and the upper source/drain pattern, the lower embedded pattern is located between the lower source/drain pattern and the upper/source drain pattern, the upper source/drain pattern includes a first upper epitaxial pattern and a second upper epitaxial pattern on the first upper epitaxial pattern, the first upper epitaxial pattern covers the sides of the two upper channel stacks and the upper surface of the lower embedded pattern, and the upper surface of the lower embedded pattern may be located at a vertical level that is higher than the lower surface of the upper inner electrode of the lowest layer among the upper inner electrodes and lower than the upper surface of the upper inner electrode of the lowest layer.

Inventors

• 양석
• 허양
• 한창용
• 하룡
• 이상문
• 손수민

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20260420

Claims (10)

1. Substructure including a lower source/drain pattern; Lower embedded pattern on the above lower structure; and It includes an upper structure on the lower buried pattern above, The above upper structure is: Upper channel stacks spaced apart from each other in a first direction, each of the upper channel stacks including upper semiconductor patterns stacked and spaced apart from each other in a second direction perpendicular to the first direction; Upper source/drain pattern between two adjacent upper channel stacks; Upper inner electrodes respectively interposed between adjacent upper semiconductor patterns among the upper semiconductor patterns; and It includes upper inner spacers interposed between each of the upper inner electrodes and the upper source/drain pattern, and The lower buried pattern is located between the lower source/drain pattern and the upper/source drain pattern, and The above upper source/drain pattern includes a first upper epitaxial pattern and a second upper epitaxial pattern on the first upper epitaxial pattern, and The first upper epitaxial pattern covers the sides of the two upper channel stacks and the upper surface of the lower embedded pattern, and A semiconductor device in which the upper surface of the lower embedded pattern is located at a vertical level that is higher than the lower surface of the upper inner electrode of the lowest layer among the upper inner electrodes and lower than the upper surface of the upper inner electrode of the lowest layer.
2. In Article 1, The above-mentioned first upper epitaxial pattern has a 'U'-shaped cross-section, and The first upper epitaxial pattern has a first thickness in the first direction on the sides of the two upper channel stacks, and The first upper epitaxial pattern has a second thickness in the second direction on the upper surface of the lower embedded pattern, A semiconductor device in which the first thickness is greater than the second thickness.
3. In Article 1, The material constituting the upper inner spacers and the material constituting the lower embedded pattern are the same semiconductor device.
4. In Paragraph 3, A semiconductor device in which at least a portion of the lower embedded pattern contacts at least a portion of the upper inner spacers and forms an integral structure.
5. In Article 1, The above first upper epitaxial pattern is a semiconductor device comprising silicon-germanium.
6. In Article 1, The above-mentioned first upper epitaxial pattern comprises a semiconductor material doped with a first N-type dopant, and The above second upper epitaxial pattern comprises a semiconductor material doped with a second N-type dopant, and A semiconductor device in which the concentration of the second dopant in the second upper epitaxial pattern is greater than the concentration of the first dopant in the first epitaxial pattern.
7. In Article 6, The above first dopant is a semiconductor device different from the above second dopant.
8. Substructure including a lower source/drain pattern; Lower embedded pattern on the above lower structure; and It includes an upper structure on the lower buried pattern above, The above upper structure is: Upper channel stacks spaced apart from each other in a first direction, each of the upper channel stacks including upper semiconductor patterns stacked and spaced apart from each other in a second direction perpendicular to the first direction; Upper source/drain pattern between two adjacent upper channel stacks; It includes upper inner electrodes interposed between adjacent upper semiconductor patterns among the above upper semiconductor patterns, and The lower buried pattern is located between the lower source/drain pattern and the upper/source drain pattern, and The above upper source/drain pattern includes a first upper epitaxial pattern and a second upper epitaxial pattern on the first upper epitaxial pattern, and The first upper epitaxial pattern has a 'U'-shaped cross-section and covers the sides of the two upper channel stacks and the upper surface of the lower embedded pattern, The first upper epitaxial pattern has a first thickness in the first direction on the sides of the two upper channel stacks, and The first upper epitaxial pattern has a second thickness in the second direction on the upper surface of the lower embedded pattern, A semiconductor device in which the first thickness is greater than the second thickness.
9. In Article 8, The upper structure further includes upper inner spacers interposed between each of the upper inner electrodes and the upper source/drain pattern, and The above first upper epitaxial pattern is a semiconductor device spaced apart from the upper inner electrodes by the upper inner spacers.
10. In Article 8, A semiconductor device in which the upper surface of the lower embedded pattern is located at a vertical level that is higher than the lower surface of the upper inner electrode of the lowest layer among the upper inner electrodes and lower than the upper surface of the upper inner electrode of the lowest layer.

Description

Semiconductor device including field effect transistor The present invention relates to a semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor. Semiconductor devices include integrated circuits composed of MOS (Metal Oxide Semiconductor) FETs. As the size and design rules of semiconductor devices gradually shrink, the scale-down of MOS FETs is also accelerating. The operating characteristics of semiconductor devices may degrade as the size of MOS FETs is reduced. Accordingly, various methods are being studied to form semiconductor devices with superior performance while overcoming the limitations associated with high integration of semiconductor devices. FIG. 1 is a plan view illustrating a logic cell of a semiconductor device according to embodiments of the present invention. FIG. 2 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 3a, FIGS. 3b, and FIGS. 3c are cross-sectional views for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 4a, FIGS. 4b, and FIGS. 4c are enlarged cross-sectional views for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 5a to 13c are drawings for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention. Embodiments of the present invention will be described below with reference to the drawings. Throughout the entire specification, the same reference numerals may refer to the same components. In this specification, the term “substantially” should be interpreted to mean not only that the described shape, angle, direction, or numerical value is mathematically or physically identical, but also that it includes manufacturing tolerances, measurement errors, or design allowances that are customary in the art. For example, “substantially identical” may mean identical within a range of manufacturing tolerances or measurement errors. For example, the tolerance range may be approximately 5%. FIG. 1 is a plan view illustrating a logic cell of a semiconductor device according to embodiments of the present invention. Referring to FIG. 1, a single height cell (SHC) comprising a semiconductor device (e.g., a stacked transistor) may be provided. For example, the semiconductor device may be a three-dimensional semiconductor device comprising a stacked transistor. Specifically, a first power line (POR1) and a second power line (POR2) may be provided on a substrate. A drain voltage, i.e., a power voltage, may be applied to either the first power line (POR1) or the second power line (POR2). A source voltage, i.e., a ground voltage, may be applied to the other of the first power line (POR1) and the second power line (POR2). A single height cell (SHC) may be defined between a first power line (POR1) and a second power line (POR2). The single height cell (SHC) may include a lower active region (LAR) and an upper active region (UAR). Either the lower active region (LAR) or the upper active region (UAR) may be a PMOSFET (P-type Metal-Oxide-Semiconductor Field Effect Transistor) region, and the other of the lower active region (LAR) and the upper active region (UAR) may be an NMOSFET (N-type Metal-Oxide-Semiconductor Field Effect Transistor) region. Accordingly, the single height cell (SHC) may have a CMOS (Complementary Metal-Oxide-Semiconductor) structure provided between the first power line (POR1) and the second power line (POR2). A lower active region (LAR) may be provided as a bottom tier on a substrate. A top active region (UAR) may be provided as a top tier on the lower active region (LAR). The lower active region (LAR) and the top active region (UAR) may be spaced apart from each other in a vertical direction. As a result, the semiconductor device is a three-dimensional semiconductor device, and transistors of the FEOL (Front End Of Line) layer can be vertically stacked. For example, a PMOSFET of the lower active region (LAR) may be provided on a substrate, and an NMOSFET of the top active region (UAR) may be stacked on the PMOSFET. A single height cell (SHC) can constitute a single logic cell. In this specification, a logic cell may refer to a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). That is, a logic cell may include logic transistors for constituting a logic element and wirings connecting the logic transistors to each other. From a planar perspective, the lower active region (LAR) and the upper active region (UAR) can overlap each other. As a result, the area of the single height cell (SHC) can be relatively smaller compared to the case where the lower active region (LAR) and the upper active region (UAR) are arranged two-dimensionally. Therefore, the integration density of the semiconductor device can be improved. FIG. 2 is a plan view for illustrating a semiconductor device according to em