KR-20260064698-A - Semiconductor devices and electronic devices

Abstract

A semiconductor device according to one embodiment of the present disclosure comprises: a first substrate formed by stacking a first semiconductor layer and a first wiring layer; a second substrate formed by stacking a second semiconductor layer and a second wiring layer, wherein the second wiring layer forms a bonding surface together with the first wiring layer; a plurality of first bonding electrodes formed on the bonding surface of the first wiring layer and each having a first bonding surface; a plurality of second bonding electrodes formed on the bonding surface of the second wiring layer and each having a second bonding surface that is bonded to the first bonding surface of the plurality of first bonding electrodes; one or more first metal layers formed between adjacent first bonding electrodes on the bonding surface of the first wiring layer and having a first opposing surface facing the second substrate that is recessed toward the first semiconductor layer side from the first bonding surface; and one or more second metal layers formed between adjacent second bonding electrodes on the bonding surface of the second wiring layer and having a second opposing surface facing the first substrate.

Inventors

• 후지이 노부토시
• 사이토 스구루

Assignees

• 소니 세미컨덕터 솔루션즈 가부시키가이샤

Dates

Publication Date

20260507

Application Date

20240815

Priority Date

20230904

Claims (18)

1. A first substrate formed by stacking a first semiconductor layer and a first wiring layer, and A second substrate formed by stacking a second semiconductor layer and a second wiring layer, wherein the second wiring layer forms a bonding surface together with the first wiring layer, and A plurality of first bonding electrodes formed on the bonding surface of the first wiring layer and each having a first bonding surface, and A plurality of second bonding electrodes each having a second bonding surface formed on the bonding surface of the second wiring layer and bonded to the first bonding surface of the plurality of first bonding electrodes, and One or more first metal layers having a first opposing surface facing the second substrate, formed between the plurality of adjacent first bonding electrodes on the bonding surface of the first wiring layer and recessed toward the first semiconductor layer side from the first bonding surface, and One or more second metal layers formed between the plurality of adjacent second bonding electrodes on the bonding surface of the second wiring layer and having a second opposing surface facing the first substrate. A semiconductor device equipped with
2. A semiconductor device according to claim 1, wherein the first substrate and the second substrate are electrically connected to each other by the joining of the plurality of first bonding electrodes and the plurality of second bonding electrodes.
3. A semiconductor device according to claim 1, wherein the first metal layer and the second metal layer have mutually equivalent potentials applied to them.
4. A semiconductor device according to claim 1, wherein a fixed potential is applied to the first metal layer and the second metal layer.
5. A semiconductor device according to claim 1, wherein the first metal layer is continuously provided to surround each of the plurality of first junction electrodes.
6. A semiconductor device according to claim 1, wherein the first metal layer is intermittently arranged to surround each of the plurality of first junction electrodes.
7. A semiconductor device according to claim 1, wherein the second metal layer is continuously provided to surround each of the plurality of second junction electrodes.
8. A semiconductor device according to claim 1, wherein the second metal layer is intermittently arranged to surround each of the plurality of second junction electrodes.
9. In claim 1, the first bonding electrode has a first electrode layer embedded in the bonding surface of the first wiring layer and a first barrier metal layer provided between the first electrode layer and the first wiring layer. A semiconductor device having the second junction electrode, the second electrode layer embedded in the junction surface of the second wiring layer, and the second barrier metal layer provided between the second electrode layer and the second wiring layer.
10. A semiconductor device according to claim 9, wherein the first metal layer, the second metal layer, the first barrier metal layer, and the second barrier metal layer are formed using the same material.
11. A semiconductor device according to claim 9, wherein the first metal layer, the second metal layer, the first barrier metal layer, and the second barrier metal layer are each formed using a metal material or a metal nitride material.
12. A semiconductor device according to claim 1, wherein the second opposing surface of the one or more second metal layers is recessed toward the second semiconductor layer side than the second bonding surface.
13. In claim 9, the second opposing surface of the one or more second metal layers is recessed toward the second semiconductor layer side than the second bonding surface, and The opposing surface of the first barrier metal layer facing the second substrate is recessed toward the first semiconductor layer side than the first bonding surface of the first bonding electrode, and A semiconductor device in which the opposing surface of the second barrier metal layer facing the first substrate is recessed toward the second semiconductor layer side than the second bonding surface of the second bonding electrode.
14. A semiconductor device according to claim 12, wherein an insulating film is laminated on the first opposing surface of the first metal layer and the second opposing surface of the second metal layer, respectively.
15. In claim 14, the first bonding electrode comprises a first electrode layer embedded in the bonding surface of the first wiring layer and a first barrier metal layer provided between the first electrode layer and the first wiring layer. The second bonding electrode has a second electrode layer embedded in the bonding surface of the second wiring layer and a second barrier metal layer provided between the second electrode layer and the second wiring layer. The opposing surface of the first barrier metal layer facing the second substrate is recessed toward the first semiconductor layer side than the first bonding surface of the first bonding electrode, and The opposing surface of the second barrier metal layer facing the first substrate is recessed toward the second semiconductor layer side than the second bonding surface of the second bonding electrode, and A semiconductor device having an insulating film laminated on the opposing surfaces of each of the first barrier metal layer and the second barrier metal layer.
16. In claim 1, the first semiconductor layer is provided with, for each pixel, a photoelectric conversion unit and a floating diffusion in which signal charge generated from the photoelectric conversion unit is accumulated. A semiconductor device having a pixel transistor that reads the signal charge of the floating diffusion in the second semiconductor layer.
17. In claim 16, the first junction electrode is electrically connected to the floating diffusion, forming a semiconductor device.
18. Equipped with a semiconductor device, The above semiconductor device is, A first substrate formed by stacking a first semiconductor layer and a first wiring layer, and A second substrate formed by stacking a second semiconductor layer and a second wiring layer, wherein the second wiring layer forms a bonding surface together with the first wiring layer, and A plurality of first bonding electrodes formed on the bonding surface of the first wiring layer and each having a first bonding surface, and A plurality of second bonding electrodes each having a second bonding surface formed on the bonding surface of the second wiring layer and bonded to the first bonding surface of the plurality of first bonding electrodes, and One or more first metal layers having a first opposing surface facing the second substrate, formed between the plurality of adjacent first bonding electrodes on the bonding surface of the first wiring layer and recessed toward the first semiconductor layer side from the first bonding surface, and One or more second metal layers formed between the plurality of adjacent second bonding electrodes on the bonding surface of the second wiring layer and having a second opposing surface facing the first substrate. An electronic device having

Description

Semiconductor devices and electronic devices The present disclosure relates to a semiconductor device and an electronic device having a plurality of semiconductor layers stacked together. For example, Patent Document 1 discloses an imaging device in which a first substrate having a plurality of sensor pixels and a second substrate having a plurality of reading circuits are electrically connected to each other by bonding electrodes provided on their respective opposing surfaces. FIG. 1 is a block diagram showing an example of the functional configuration of an imaging device according to one embodiment of the present disclosure. Figure 2 is a planar schematic diagram showing the schematic configuration of the imaging device shown in Figure 1. Figure 3 is a schematic diagram showing a cross-sectional configuration along the line A-A' shown in Figure 2. Figure 4 is an equivalent circuit diagram of the pixel sharing unit shown in Figure 1. FIG. 5 is a diagram showing an example of a connection mode between a plurality of pixel sharing units and a plurality of vertical signal lines. FIG. 6 is a schematic cross-sectional view showing an example of the specific configuration of the imaging device shown in FIG. 3. FIG. 7a is a schematic diagram showing an example of the planar configuration of the main part of the first substrate shown in FIG. 6. FIG. 7b is a schematic diagram showing the planar configuration of the pad portion together with the main portion of the first substrate shown in FIG. 7a. FIG. 8 is a schematic diagram showing an example of a horizontal planar configuration with respect to the main surface of the second substrate (semiconductor layer) shown in FIG. 6. FIG. 9 is a schematic diagram showing an example of a planar configuration of a pixel circuit and a main part of a first substrate together with the first wiring layer shown in FIG. 6. FIG. 10a is a schematic cross-sectional diagram illustrating the detailed configuration of the bonding surface between the first substrate and the second substrate shown in FIG. 6. FIG. 10b is a schematic cross-sectional diagram illustrating the misalignment at the bonding surface between the first substrate and the second substrate. FIG. 11a is a schematic cross-sectional diagram illustrating the configuration of the bonding surface of two substrates as a comparative example. FIG. 11b is a schematic cross-sectional diagram illustrating the misalignment of two substrates in the configuration shown in FIG. 11a. FIG. 12a is a schematic cross-sectional diagram illustrating the configuration of the bonding surface of two substrates as a comparative example. FIG. 12b is a schematic cross-sectional diagram illustrating the misalignment of two substrates in the configuration shown in FIG. 12a. FIG. 13a is a planar schematic diagram showing an example of the layout of a plurality of bonding electrodes and shield electrodes at the bonding surface of each of the first substrate and the second substrate. FIG. 13b is a planar schematic diagram showing another example of the layout of a plurality of bonding electrodes and shield electrodes at the bonding surface of each of the first substrate and the second substrate. FIG. 13c is a planar schematic diagram showing another example of the layout of a plurality of bonding electrodes and shield electrodes at the bonding surface of each of the first substrate and the second substrate. FIG. 14a is a cross-sectional schematic diagram illustrating the manufacturing process of a plurality of bonding electrodes and shield electrodes at the bonding surface of the first substrate and the second substrate shown in FIG. 10a. FIG. 14b is a cross-sectional schematic diagram showing the process following FIG. 14a. FIG. 14c is a schematic cross-sectional view showing the process following FIG. 14b. FIG. 14d is a schematic cross-sectional view showing the process following FIG. 14c. FIG. 14e is a schematic cross-sectional view showing the process following FIG. 14d. FIG. 14f is a cross-sectional schematic diagram showing the process following FIG. 14e. FIG. 14g is a schematic cross-sectional view showing the process following FIG. 14f. FIG. 14h is a schematic cross-sectional diagram showing the process following FIG. 14g. FIG. 15 is a schematic diagram for explaining the path of input signals, etc. to the imaging device shown in FIG. 3. FIG. 16 is a schematic diagram for explaining the signal path of the pixel signal of the imaging device shown in FIG. 3. FIG. 17a is a schematic cross-sectional diagram illustrating the manufacturing process of a plurality of bonded electrodes and shield electrodes according to Variant Example 1 of the present disclosure. FIG. 17b is a cross-sectional schematic diagram showing the process following FIG. 17a. FIG. 17c is a cross-sectional schematic diagram showing the process following FIG. 17b. FIG. 17d is a schematic cross-sectional view showing the process following FIG. 17c. FIG. 18 is a schematic cross-sec