KR-20260064705-A - Method for manufacturing a semiconductor device, and insulating resin material

KR20260064705AKR 20260064705 AKR20260064705 AKR 20260064705AKR-20260064705-A

Abstract

In a method for manufacturing a semiconductor device, a semiconductor member (10) having micro-bumps, such as minute copper fillers (12) and solder bumps (13), is prepared on a semiconductor wafer (11). Then, an underfill material is applied and spread over the semiconductor member (10) to cover the copper fillers (12) and solder bumps (13), and then cured. As a result, an insulating resin layer (20) thicker than the height of the connection portion (14) formed by the copper fillers (12) and solder bumps (13) is formed. Afterward, the thick insulating resin layer (20) is ground with a CMP device to expose the surface (13a) of the solder bumps (13A) from the insulating resin layer. According to this method, the uniformity of the height of the bumps (13) and the smoothness of the surface of the bumps (13) can be improved. As the smoothness of the surface is improved, it is also difficult for voids to occur. In addition, since each bump (13) is covered by an insulating resin layer (20), it becomes difficult for bridges to form. This method can be applied to CoW and WoW.

Inventors

우에노 게이코
가토 사다아키
강동철

Assignees

가부시끼가이샤 레조낙

Dates

Publication Date: 20260507
Application Date: 20240904
Priority Date: 20230905

Claims (14)

A process for preparing a composite having a semiconductor substrate, a connection portion provided on a main surface of the semiconductor substrate, and an insulating resin layer provided on the main surface of the semiconductor substrate to cover the connection portion, and The above-mentioned composite has a process for grinding the insulating resin layer, and A method for manufacturing a semiconductor device, wherein in the grinding process above, the insulating resin layer is ground so as to expose the surface of the connection portion.
In claim 1, A method for manufacturing a semiconductor device, wherein in the above grinding process, a part of the connection portion is ground together with the insulating resin layer.
In claim 1 or claim 2, The above connection portion includes a connection terminal provided on the main surface of the semiconductor substrate and a bump provided on the connection terminal, and A method for manufacturing a semiconductor device, wherein in the grinding process above, a portion of the bump is ground so that the surface of the bump is exposed from the insulating resin layer.
In any one of claims 1 to 3, The process of preparing the above-mentioned composite is, A process for preparing a semiconductor member having the above semiconductor substrate and the above connection portion, and The process includes forming an insulating resin layer by providing a liquid insulating resin material on the main surface of the semiconductor substrate to cover the connection portion of the semiconductor member. A method for manufacturing a semiconductor device in which the insulating resin layer is thicker than the height of the connection portion when provided on the semiconductor substrate.
In any one of claims 1 to 3, The process of preparing the above-mentioned composite is, A process for preparing a semiconductor member having the above semiconductor substrate and the above connection portion, and The process includes forming the insulating resin layer by attaching a film-shaped insulating resin material to the main surface of the semiconductor substrate to cover the connection portion of the semiconductor member. A method for manufacturing a semiconductor device in which the insulating resin layer is thicker than the height of the connection portion when attached to the semiconductor substrate.
In claim 4 or claim 5, The process of preparing the above-mentioned composite is, A method for manufacturing a semiconductor device, further comprising a process of performing a curing treatment on the insulating resin layer of the composite before the grinding process.
In any one of claims 1 to 6, A method for manufacturing a semiconductor device, wherein in the grinding process above, the insulating resin layer is ground using at least one of a grinder, a surface planer, and a CMP device.
In any one of claims 1 to 7, A method for manufacturing a semiconductor device, wherein the insulating resin layer comprises an epoxy resin, a curing agent, and an inorganic filler.
In any one of claims 1 to 7, A method for manufacturing a semiconductor device, wherein the insulating resin layer comprises an epoxy resin, a curing agent, and a flux.
In any one of claims 1 to 9, A process of reorganizing the bonded body into a plurality of semiconductor chips after grinding the insulating resin layer, and A method for manufacturing a semiconductor device, further comprising a process of mounting at least one semiconductor chip among the plurality of semiconductor chips on a substrate.
In claim 10, The above substrate is provided with a terminal connected to the connection portion of the above assembly, and A method for manufacturing a semiconductor device, wherein the above terminal has a surface treatment performed for connecting to the solder of the above connection portion.
In claim 10 or claim 11, The above substrate is a semiconductor wafer having other connection parts, and A method for manufacturing a semiconductor device in which, in the above-described mounting process, a connection portion of at least one semiconductor chip is connected to another connection portion of the semiconductor wafer.
In any one of claims 1 to 9, The method further comprises a process of bonding the first semiconductor wafer, which is the bonded body after grinding the insulating resin layer, to a second semiconductor wafer having another connection portion, and A method for manufacturing a semiconductor device in which, in the bonding process above, the connection portion of the first semiconductor wafer is connected to the other connection portion of the second semiconductor wafer.
A process for preparing a composite having a semiconductor substrate, a connection portion provided on a main surface of the semiconductor substrate, and an insulating resin layer provided on the main surface of the semiconductor substrate to cover the connection portion, and An insulating resin material used to form the insulating resin layer in a method for manufacturing a semiconductor device comprising a process of grinding the insulating resin layer of the assembly so as to expose the surface of the connection portion.

Description

Method for manufacturing a semiconductor device, and insulating resin material The present disclosure relates to a method for manufacturing a semiconductor device and an insulating resin material. Flip-chip junctions are known in which conductive protrusions called bumps are formed on a semiconductor chip to directly connect the semiconductor chip to a wiring circuit board. Attempts have been made to multi-layer semiconductor chips into 4, 8, or 12 layers using such flip-chip junctions, and accordingly, the height of the bumps tends to be low and the diameter of the bumps tends to be small (see, for example, Non-patent Literature 1 and Non-patent Literature 2). FIG. 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. FIG. 2 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 4(a) to FIGS. 4(d) are cross-sectional views showing the case where the manufacturing method of a semiconductor device according to the present embodiment is applied to a CoW (first modified example). FIGS. 5(a) to FIGS. 5(c) are cross-sectional views showing the case where the manufacturing method of a semiconductor device according to the present embodiment is applied to WoW (second modified example). Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, identical or substantial parts are denoted by the same reference numerals, and redundant descriptions are omitted. Furthermore, positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings unless otherwise specifically stated. Additionally, the dimensional ratios in the drawings are not limited to the ratios shown. In this specification, the term "layer" includes, in addition to the structure of shape formed on the entire surface when observed as a plan view, the structure of shape formed on a part thereof. In this specification, the term "process" includes not only independent processes but also processes that cannot be clearly distinguished from other processes, provided that the intended function of the process is achieved. In this specification, numerical ranges indicated by "~" represent a range that includes the values listed before and after "~" as minimum and maximum values, respectively. In numerical ranges described stepwise in this specification, the upper or lower limit of a numerical range in any step may be substituted with the upper or lower limit of a numerical range in another step. In numerical ranges described in this specification, the upper or lower limit of said numerical range may be substituted with the values shown in the examples. With reference to FIGS. 1 to 3, a method for manufacturing a semiconductor device according to the present embodiment will be described. FIGS. 1, FIGS. 2 and FIGS. 3 are schematic cross-sectional views showing the method for manufacturing a semiconductor device in sequence. First, as shown in FIG. 1 (a), a semiconductor substrate (11) and a semiconductor member (10) having a plurality of connection terminals (12) and a plurality of bumps (13) provided on a main surface (11a) of the semiconductor substrate (11) are prepared. The semiconductor substrate (11) is, for example, an elemental semiconductor composed of elements of the same type such as silicon or germanium, or a semiconductor substrate including a compound semiconductor such as gallium arsenide or indium phosphide. In this embodiment, the case where the semiconductor substrate (11) is a semiconductor wafer is described as an example, but the semiconductor substrate (11) may be a semiconductor chip. The thickness of the semiconductor substrate (11) is, for example, 10 μm to 800 μm. Each of the bumps (13) is provided on a corresponding connection terminal (12). The connection terminal (12) and the bumps (13) may be metal layers containing one or more metals selected from, for example, gold, silver, copper, solder, nickel, tin, and lead. The main component of the solder may be, for example, tin-silver, tin-lead, tin-bismuth, tin-copper, or tin-silver-copper. The metal constituting the connection terminal (12) and the bumps (13) may be gold, silver, copper, or solder; silver, copper, or solder; copper or solder; or solder. The connection terminal (12) and the bumps (13) may be metal layers formed by plating. The connection terminal (12) and the bumps (13) may be a single layer or may include multiple metal layers. For example, the connection terminal (12) may be a copper filler, and the bump (13) may be a solder bump. The diameter of each of the connection terminal (12) and the bump (13) may be, for example, 20 μm or less, or 10 μm or less. The total height of the connection portion (