KR-20260064716-A - Method for forming a microelectronic device, and related microelectronic device and memory device

Abstract

The microelectronic device comprises a memory cell, a hierarchical digit line (HDL) structure, and a sense amplifier (SA) device. The memory cell is located within an array area and includes an access device and a storage node device that is vertically positioned over the access device and coupled thereto. The HDL structure is located within an array area and is vertically positioned over the memory cell and coupled thereto. The HDL structure includes a lower section, an upper section that is vertically positioned over the lower section and is at least partially horizontally offset therefrom, and an intermediate section that extends vertically from and between the lower and upper sections. The SA device is located within an array area and is vertically positioned over the HDL structure and coupled thereto. Related methods, memory devices, and electronic systems are also described.

Inventors

• 심섹-에게, 파트마 알줌
• 류, 하이타오
• 데이콕, 데이비스 에이.

Assignees

• 마이크론 테크놀로지, 인크.

Dates

Publication Date

20260507

Application Date

20240809

Priority Date

20240617

Claims (20)

1. As a microelectronic device, As memory cells within the array area, each Access device; and A storage node device positioned vertically and horizontally above the access device and coupled thereto The memory cell including; A hierarchical digit line (HDL) structure located within the array area, positioned vertically above the memory cell, and coupled thereto, each Subsection; An upper section that is positioned vertically over the lower section and is at least partially offset horizontally from it; and An intermediate section extending vertically from and between the above lower section and the above upper section The above HDL structure including; and A sensing amplifier (SA) device located within the array area, positioned vertically above the HDL structure, and coupled thereto A microelectronic device comprising
2. In paragraph 1, the memory cell additionally each A cell contact coupled to the access device and extending vertically downward from it; and A redistributed material (RDM) structure vertically interposed between the cell contact and the storage node device and in contact therewith A microelectronic device comprising
3. A microelectronic device according to paragraph 2, further comprising a digit line contact vertically interposed between the memory cell and the HDL structure and in contact therewith, wherein the digit line contact is individually coupled to the access device of each memory cell among the memory cells and extends vertically upward therefrom.
4. In any one of paragraphs 1 to 3, the HDL structure is, The first HDL structure; and A second HDL structure extending horizontally parallel to the first HDL structure in a first direction and alternating horizontally with the first HDL structure in a second direction orthogonal to the first direction Includes, At least one lower section of the second HDL structure is substantially horizontally overlapped with at least one upper section of the first HDL structure in the first direction, and A microelectronic device in which at least one upper section of the second HDL structure is substantially horizontally overlapped with at least one lower section of the first HDL structure in the first direction.
5. In paragraph 4, The first HDL structure comprises a first base HDL structure and a first complementary HDL structure, and a portion of the SA device is individually coupled to each of the first base HDL structures and each of the first complementary HDL structures; A microelectronic device wherein the second HDL structure comprises a second base HDL structure and a second complementary HDL structure, and a part other of the SA device is individually coupled to each of the second base HDL structures and each of the second complementary HDL structures.
6. In any one of paragraphs 1 to 3, the SA device transistor; and A conductive routing structure positioned vertically above and coupled thereto, wherein the transistor is vertically interposed between the conductive routing structure and the HDL structure. A microelectronic device comprising
7. In any one of paragraphs 1 to 3, the SA device transistor; and A conductive routing structure that is positioned vertically above the transistor and coupled thereto, wherein the conductive routing structure is vertically interposed between the transistor and the HDL structure. A microelectronic device comprising
8. A microelectronic device according to any one of claims 1 to 3, further comprising a sub-word line driver (SWD) device located within a word line (WL) exit zone that is vertically positioned above the HDL structure and horizontally adjacent to the array zone, wherein the SWD device is coupled to the WL structure coupled to the memory cell.
9. In any one of paragraphs 1 through 3, A capacitor device located in a peripheral zone horizontally adjacent to the array zone; and An additional control logic device positioned vertically above the HDL structure and located within the peripheral area, wherein at least a portion of the additional control logic device is coupled to the capacitor device. A microelectronic device that additionally includes
10. As a method for forming a microelectronic device, A step of forming a first microelectronic device structure comprising an access device and an array region having memory cells each comprising a capacitor vertically positioned above the access device and coupled thereto; A step of vertically inverting the above-mentioned first microelectronic device structure; A step of vertically inverting the first microelectronic device structure and then forming a contact structure within the array area and coupled to the memory cell; A step of forming a hierarchical digit line (HDL) structure that is located within the array area, is vertically positioned over the contact structure, and is coupled thereto, wherein the HDL structure comprises a lower section, an upper section that is vertically positioned over the lower section and is horizontally offset therefrom, and an intermediate section vertically positioned between the lower section and the upper section, respectively. A step of attaching a second microelectronic device structure including a sensing amplifier (SA) device on the HDL structure, wherein after attaching the second microelectronic device structure on the HDL structure, the SA device is located within the array area; and A step of combining the above SA device with the above HDL structure A method including
11. In claim 10, the step of forming the first microelectronic device structure A word line (WL) exit region comprising a portion of a WL structure coupled to the memory cell; and A peripheral area including an additional capacitor located vertically above the capacitor of each of the memory cells above. Step of forming the first microelectronic device structure to additionally include A method including
12. In claim 11, the method further includes the step of forming the second microelectronic device structure to additionally include a sub-word line driver (SWD) device and an additional control logic device horizontally offset from the SA device, wherein After attaching the second microelectronic device structure to the HDL structure, the SWD device is located within the array area, and A method in which, after attaching the second microelectronic device structure to the HDL structure, the additional control logic device is located within the surrounding area.
13. In Clause 12, after attaching the second microelectronic device structure onto the HDL structure, A step of coupling the above SWD device to the above WL structure; and A step of coupling at least a portion of the above additional control logic device to the above additional capacitor. A method that additionally includes
14. In any one of claims 10 to 13, the step of forming the HDL structure Odd HDL structures; and Even HDL structures extending horizontally parallel to odd HDL structures in a first direction and alternating horizontally with odd HDL structures in a second direction orthogonal to the first direction The step of forming the HDL structure to include, At least one lower section of the even HDL structure is substantially horizontally overlapped with at least one upper section of the odd HDL structure in the first direction, and A method in which at least one upper section of the even HDL structure is substantially horizontally overlapped with at least one lower section of the odd HDL structure in the first direction.
15. A method according to any one of claims 10 to 13, wherein the step of attaching a second microelectronic device structure on the HDL structure comprises the step of bonding a dielectric oxide material of the second microelectronic device structure to an additional oxide dielectric material formed on the HDL structure.
16. A method according to any one of claims 10 to 13, wherein the step of coupling the SA device to the HDL structure comprises, after attaching the second microelectronic device structure to the HDL structure, forming an additional contact structure that extends vertically between the SA device and the HDL structure and couples them.
17. A method according to any one of claims 10 to 13, further comprising the step of forming a back-end-of-line (BEOL) structure vertically on the SA device after coupling the SA device to the HDL structure.
18. As a memory device, As an array section, A memory cell comprising an access device positioned vertically above a capacitor and coupled thereto; A word line (WL) structure that is positioned vertically over the capacitor of the memory cell and extends horizontally parallel to the first direction; A hierarchical digit line (HDL) structure that is positioned vertically above the above WL structure and coupled to the access device of the memory cell, extending parallel in a second direction orthogonal to the first direction and each Section 1; A second section positioned vertically above the first section and horizontally offset therefrom in the second direction; A third section extending vertically from the first section to the second section. The above HDL structure including; A sensing amplifier (SA) device positioned vertically and horizontally on the above HDL structure and coupled thereto The array section including; and As a WL exit zone horizontally adjacent to the array zone in the above second direction, A portion of the above WL structure; and A sub-word line driver (SWD) device that is positioned vertically and horizontally over a portion of the above WL structure and coupled thereto The WL exit zone including A memory device including
19. In paragraph 18, the surrounding area horizontally adjacent to the array area in the first direction is additionally included, wherein the surrounding area is An additional capacitor when vertically superimposed with the capacitor of the above memory cell; and An additional control logic device positioned vertically above the additional capacitor and coupled thereto A memory device including
20. In claim 18 or 19, the above HDL structure Odd HDL structures; and Even HDL structures alternating horizontally with the odd HDL structures in the first direction Includes, Each of the first sections of the even HDL structures is horizontally overlapped with each of the second sections of the odd HDL structures in the second direction, and A memory device in which each of the second sections of the even HDL structures is horizontally overlapped with each of the first sections of the odd HDL structures in the second direction.

Description

Method for forming a microelectronic device, and related microelectronic device and memory device Claim of priority This application claims the benefit of the filing date of U.S. Patent Application Serial No. 63/580,922 (filing date: September 6, 2023, title of invention: 'METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND MEMORY DEVICES') and also claims the benefit of the filing date of U.S. Patent Application Serial No. 18/745,943 (filing date: June 17, 2024, title of invention: 'METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND MEMORY DEVICES'), the full contents of which are incorporated herein by reference. Technology field The present disclosure relates, in various embodiments, generally to the field of designing and manufacturing microelectronic devices. More specifically, the present disclosure relates to a method for forming a microelectronic device and a memory device, and to related microelectronic devices, memory devices, and electronic systems. Microelectronic device designers often seek to increase the level or density of feature integration within microelectronic devices by reducing the dimensions of individual features and decreasing the spacing between adjacent features. Furthermore, microelectronic device designers often aim to design architectures that are not only compact and offer performance advantages, but are also simple, easy to design, and inexpensive to manufacture. An example of a microelectronic device is a memory device. Memory devices are typically provided as internal integrated circuits in computers or other electronic devices. There are many types of memory devices, including but not limited to volatile memory devices. One type of volatile memory device is a dynamic random access memory (DRAM) device. A DRAM device may include a memory array comprising DRAM cells arranged in rows extending in a first horizontal direction and columns extending in a second horizontal direction. In one design configuration, an individual DRAM cell includes an access device (e.g., a transistor) and a storage node device (e.g., a capacitor) electrically connected to the access device. The DRAM cells of the DRAM device are electrically accessible through digit lines and word lines arranged along the rows and columns of the memory array and communicate electrically with control logic devices within the basic control logic structure of the DRAM device. Control logic devices within the basic control logic structure located beneath the memory array of a DRAM device have been used to control operations on the DRAM cells of the DRAM device. The control logic devices of the basic control logic structure may be provided to communicate electrically with the digit lines and word lines coupled to the DRAM cells through routing and contact structures. Unfortunately, processing conditions (e.g., temperature, pressure, material) for forming the memory array above the basic control logic structure may limit the configuration and performance of the control logic devices within the basic control logic structure. Furthermore, the quantity, dimensions, and arrangement of different control logic devices used within the basic control logic structure may also undesirably hinder a reduction in the size of the memory device (e.g., horizontal footprint) and/or an improvement in the performance of the DRAM device (e.g., faster memory cell on/off speeds, lower threshold switching voltage requirements, faster data transfer rates, lower power consumption). In some embodiments, the microelectronic device comprises a memory cell, a hierarchical digit line (HDL) structure, and a sense amplifier (SA) device. The memory cell is located within an array area and includes an access device and a storage node device that is vertically positioned over the access device and coupled thereto. The HDL structure is located within an array area and is vertically positioned over the memory cell and coupled thereto. The HDL structure includes a lower section, an upper section that is vertically positioned over the lower section and is at least partially horizontally offset therefrom, and an intermediate section that extends vertically from and between the lower and upper sections. The SA device is located within an array area and is vertically positioned over the HDL structure and coupled thereto. In an additional embodiment, a method for forming a microelectronic device comprises the step of forming a first microelectronic device structure comprising an access device and an array region having memory cells each comprising a capacitor that is vertically positioned over the access device and coupled thereto. The first microelectronic device structure is vertically inverted. After vertically inverting the first microelectronic device structure, a contact structure is formed within the array region and coupled to the memory cell. A hierarchical digit line (HDL) structure is withi