KR-20260064735-A - Record processing using queue and thread identification

Abstract

Various embodiments provide processing a write request in a memory system based on a queue identifier and a thread identifier associated with the write request. In particular, various embodiments utilize the queue identifier and memory address information included in the write request to separate and associate such write request with a thread (e.g., a virtual thread) tracked by the memory system, and can combine multiple write requests associated with a single thread into a single (larger) write for a sequence of blocks.

Inventors

• 버트, 루카

Assignees

• 마이크론 테크놀로지, 인크.

Dates

Publication Date

20260507

Application Date

20240718

Priority Date

20230906

Claims (20)

1. In the system, A plurality of submission queues, wherein each of the plurality of submission queues is associated with a corresponding queue identifier, and each queue identifier is associated with at least one hardware processor core of a host system; memory device; and A processing device configured to be coupled to the memory device in an operable state and to perform tasks, wherein the tasks are A task of receiving a set of command requests from a host system, wherein each individual command request within the set of command requests includes an individual queue identifier and is stored in an individual submission queue of a plurality of submission queues associated with the individual queue identifier; A task of obtaining a selected write request including a selected memory address from a selected submission queue among the plurality of submission queues, wherein the selected submission queue is associated with a selected queue identifier; Based on the selected memory address and the selected queue identifier, the task of searching for a selected thread identifier associated with the selected memory address in a thread trace data structure; and In response to finding the selected thread identifier in the thread trace data structure above, The task of causing the above selection record request to be processed based on the above selection thread identifier; and A system comprising the operation of updating the thread trace data structure based on the above-mentioned selection record request, the above-mentioned selection memory address, and the above-mentioned selection thread identifier.
2. In paragraph 1, the operation of causing the selection record request to be performed based on the selection thread identifier is, A system comprising the operation of causing record data within a selection record request to be written to a data storage area of the memory device associated with the selection thread identifier.
3. In paragraph 1, the above operations are, In response to the failure to find the selected thread identifier in the above thread trace data structure, The task of determining a new thread identifier for the above selection record request; The task of causing the above selection record request to be performed based on the above new thread identifier; and A system comprising the operation of updating the thread trace data structure based on the above-mentioned selection record request, the above-mentioned selection memory address, and the above-mentioned new thread identifier.
4. A system according to claim 1, wherein the thread trace data structure comprises an entry set, and each entry in the entry set stores the last memory address associated with a different pair of queue identifiers and thread identifiers.
5. In claim 1, the task of searching the thread trace data structure for the selected thread identifier based on the selected memory address and the selected queue identifier is, For each individual entry of the thread trace data structure associated with the selection queue identifier, the task of determining whether the last memory address stored in the individual entry precedes the selection memory address; and A system comprising, in response to determining that the last memory address precedes the selected memory address, determining that the individual thread identifier associated with the individual entry is the selected thread identifier.
6. In claim 1, the task of searching the thread trace data structure for the selected thread identifier based on the selected memory address and the selected queue identifier is, The task of determining that no entry in the thread trace data structure associated with the above selection queue identifier stores the first last memory address preceding the above selection memory address; and In response to determining that no entry in the thread trace data structure associated with the above selection queue identifier stores the first last memory address preceding the above selection memory address, For individual entries of the thread trace data structure associated with other queue identifiers, the task of determining whether the second last memory address stored in the individual entry precedes the selected memory address; and A system comprising, in response to determining that the second last memory address precedes the selected memory address, determining that the individual thread identifier associated with the individual entry is the selected thread identifier.
7. In paragraph 1, the above operations are, The task of determining whether the above-mentioned selected thread identifier satisfies a set of pruning criteria; and A system comprising the operation of updating a thread trace data structure to remove one or more entries associated with the selected thread identifier from the thread trace data structure in response to determining that the selected thread identifier satisfies the set of pruning criteria.
8. In paragraph 1, the operation of causing the selection record request to be performed based on the selection thread identifier is, A system comprising the operation of adding the selected record request to a list of record requests associated with the selected thread identifier.
9. In paragraph 8, the above tasks are, A task to determine whether a set of conditions for executing a record request within the record request list associated with the above-mentioned selected thread identifier is satisfied; and A system comprising the operation of executing at least some of the record requests in the record request list associated with the selected thread identifier in response to determining that a set of conditions for executing a record request in the record request list associated with the selected thread identifier is satisfied.
10. In at least one non-transient machine-readable storage medium comprising instructions, said instructions, when executed by a processing device of a memory subsystem, cause said processing device to perform operations, said operations, said operations, A task of receiving a set of command requests from a host system, wherein the memory subsystem comprises a plurality of submission queues, each of the plurality of submission queues is associated with a corresponding queue identifier, each queue identifier is associated with at least one hardware processor core of the host system, and each individual command request within the set of command requests comprises an individual queue identifier and is stored in an individual submission queue of the plurality of submission queues associated with the individual queue identifier; A task of obtaining a selected write request including a selected memory address from a selected submission queue among the plurality of submission queues, wherein the selected submission queue is associated with a selected queue identifier; Based on the selected memory address and the selected queue identifier, the task of searching for a selected thread identifier associated with the selected memory address in a thread trace data structure; and In response to the failure to find the selected thread identifier in the above thread trace data structure, The task of determining a new thread identifier for the above selection record request; The task of causing the above selection record request to be performed based on the above new thread identifier; and At least one non-transient machine-readable storage medium comprising the operation of updating the thread trace data structure based on the above-mentioned selection record request, the above-mentioned selection memory address, and the above-mentioned new thread identifier.
11. In paragraph 10, the operation of causing the above selection record request to be performed based on the above new thread identifier is, The operation includes causing record data within the above-mentioned selection record request to be recorded in a data storage area of a memory device of the above-mentioned memory subsystem, wherein the data storage area is at least one non-transient machine-readable storage medium associated with the new thread identifier.
12. In Clause 10, the above tasks are, In response to finding the selected thread identifier in the thread trace data structure above, The task of causing the above selection record request to be processed based on the above selection thread identifier; and At least one non-transient machine-readable storage medium comprising the operation of updating the thread trace data structure based on the above-mentioned selection record request, the above-mentioned selection memory address, and the above-mentioned selection thread identifier.
13. In paragraph 10, the thread trace data structure comprises an entry set, and each entry in the entry set stores the last memory address associated with a different pair of queue identifiers and thread identifiers, at least one non-transient machine-readable storage medium.
14. In paragraph 10, the operation of searching for the selected thread identifier in the thread trace data structure based on the selected memory address and the selected queue identifier is, For each individual entry of the thread trace data structure associated with the selection queue identifier, the task of determining whether the last memory address stored in the individual entry precedes the selection memory address; and At least one non-transient machine-readable storage medium comprising, in response to determining that the last memory address precedes the selected memory address, determining that the individual thread identifier associated with the individual entry is the selected thread identifier.
15. In paragraph 10, the operation of searching for the selected thread identifier in the thread trace data structure based on the selected memory address and the selected queue identifier is, The task of determining that no entry in the thread trace data structure associated with the above selection queue identifier stores the first last memory address preceding the above selection memory address; and In response to determining that no entry in the thread trace data structure associated with the above selection queue identifier stores the first last memory address preceding the above selection memory address, For individual entries of the thread trace data structure associated with other queue identifiers, the task of determining whether the second last memory address stored in the individual entry precedes the selected memory address; and At least one non-transient machine-readable storage medium comprising, in response to determining that the second last memory address precedes the selected memory address, determining that the individual thread identifier associated with the individual entry is the selected thread identifier.
16. In Clause 10, the above tasks are, A task to determine whether the above-mentioned selected thread identifier satisfies a set of pruning criteria; and At least one non-transient machine-readable storage medium comprising the operation of updating the thread trace data structure to remove one or more entries associated with the selected thread identifier from the thread trace data structure in response to determining that the selected thread identifier satisfies the set of pruning criteria.
17. In paragraph 10, the operation of causing the above-mentioned selection record request to be performed based on the above-mentioned selection thread identifier is, At least one non-transient machine-readable storage medium comprising the operation of adding the selected record request to a list of record requests associated with the selected thread identifier.
18. In Paragraph 17, the above-mentioned tasks are, A task to determine whether a set of conditions for executing a record request within the record request list associated with the above-mentioned selected thread identifier is satisfied; and At least one non-transient machine-readable storage medium comprising an operation to execute at least some of the write requests in the list of write requests associated with the selected thread identifier in response to determining that a set of conditions for executing a write request in the list of write requests associated with the selected thread identifier is satisfied.
19. In terms of method, A step of receiving a set of command requests from a host system in a memory subsystem, wherein the memory subsystem comprises a plurality of submission queues, each submission queue of the plurality of submission queues is associated with a corresponding queue identifier, each queue identifier is associated with at least one hardware processor core of the host system, and each individual command request in the set of command requests comprises an individual queue identifier and is stored in an individual submission queue of the plurality of submission queues associated with the individual queue identifier; and The method comprises the step of scanning one or more of the plurality of submission queues for a command request to be executed by the processing device of the memory subsystem, wherein the scanning step is From the selected submission queue associated with the selected queue identifier among the plurality of submission queues above, a selected write request including a selected memory address is obtained, and Based on the above-mentioned selected memory address and the above-mentioned selected queue identifier, search for the selected thread identifier associated with the above-mentioned selected memory address in the thread trace data structure, and In response to finding the selected thread identifier in the thread trace data structure above, The above selection record request is processed based on the above selection thread identifier, and A method configured to update the thread trace data structure based on the above-mentioned selection record request, the above-mentioned selection memory address, and the above-mentioned selection thread identifier.
20. In paragraph 19, the scanning step above is, In response to the failure to find the selected thread identifier in the above thread trace data structure, Determine a new thread identifier for the above selection record request, and The above selection record request is performed based on the above new thread identifier, and A method configured to update the thread trace data structure based on the above-mentioned selection record request, the above-mentioned selection memory address, and the above-mentioned new thread identifier.

Description

Record processing using queue and thread identification Claim of priority This application claims the benefit of priority to U.S. provisional application serial number 63/536,818 filed on September 6, 2023, the entire said provisional application is incorporated herein by reference. Technology field Exemplary embodiments of the present disclosure generally relate to memory devices, and more specifically, to processing a write request in a memory system based on a queue identifier and a thread identifier associated with the write request. A memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can use the memory subsystem to store data in memory devices and read data from memory devices. The present disclosure will be more fully understood from the specific details for carrying out the invention given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be construed as limiting the present disclosure to specific embodiments, but are for illustrative and illustrative purposes only. FIG. 1 is a block diagram illustrating an exemplary computing system including a memory subsystem according to some embodiments of the present disclosure. FIG. 2 is a drawing illustrating an exemplary architecture of a host system and a memory subsystem according to some embodiments of the present disclosure. FIG. 3 illustrates an example of processing record requests of an exemplary request data stream according to some embodiments of the present disclosure. FIGS. 4 and 5 are flowcharts of exemplary methods for processing write requests in a memory system based on queue identifiers and thread identifications associated with write requests, according to some embodiments of the present disclosure. FIG. 6 is a block diagram of an exemplary computer system in which embodiments of the present disclosure can operate. Aspects of the present disclosure relate to processing write requests in a memory system (e.g., a memory subsystem) based on queue identifiers and thread identifications associated with the write requests. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. Generally, a host system may utilize a memory subsystem comprising one or more memory components, such as a memory device that stores data. The host system may transmit access requests to the memory subsystem to, for example, store data in the memory subsystem and read data from the memory subsystem. The host system transmits access requests (e.g., write commands, read commands) to the memory subsystem to, for example, store data on a memory device in the memory subsystem, read data from a memory device on the memory subsystem, or write/read configurations (e.g., submission and completion queues) to a memory device on the memory subsystem. Data to be read or written, as specified by a host request (e.g., a data access request or a command request), is hereinafter referred to as 'host data'. A host request may include logical address information (e.g., a logical block address (LBA), a namespace) for the host data, which is the location where the host system is associated with the host data. The logical address information (e.g., an LBA, a namespace) may be part of the metadata for the host data. The metadata may also include error handling data (e.g., an error-correcting code (ECC) codeword, a parity code), data versions (e.g., used to distinguish the time of creation of the written data), valid bitmaps (where LBAs or logical transfer units contain valid data), etc. The memory subsystem may initiate media management operations, such as write operations, on host data stored in a memory device. For example, the firmware of the memory subsystem may rewrite previously written host data from a location in the memory device to a new location as part of a garbage collection management operation. For example, data rewritten as initiated by the firmware is referred to as 'garbage collection data' below. Hereinafter, 'user data' generally refers to host data and garbage collection data. Hereinafter, 'system data' refers to data generated and/or maintained by the memory subsystem for media management and for performing operations in response to host requests. Examples of system data include, but are not limited to, system tables (e.g., logical-physical memory address mapping tables (referred to herein as L2P tables), data from logging, scratchpad data, etc.). Generally, garbage collection (GC) involves the task of managing memory utilization in NAND memory devices. When available storage space in a NAND memory device becomes insufficient, GC can recover available storage space to enable the writing of new host data. During