KR-20260064744-A - INTERCONNECT STRUCTURES

Abstract

Representative technologies and devices including process steps can be used to mitigate unwanted dishing and dielectric erosion within conductive interconnect structures. For example, a buried layer can be added to dished or eroded surfaces to remove unnecessary dishing or voids and form a flat junction surface. Additional technologies and devices including process steps can be used to form desired openings within conductive interconnect structures, which may have a predetermined or desired volume relative to the volume of the conductive material of the interconnect structure. Each of these technologies, devices, and processes enables the use of conductive interconnect structures with larger diameters, larger volumes, or mixed sizes at the junction surface of the bonded die or wafer.

Inventors

• 유조 사이프리안 에메카
• 파운틴 주니어 가이우스 길맨
• 테일 제레미 알프레드

Assignees

• 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드

Dates

Publication Date

20260507

Application Date

20191021

Priority Date

20191018

Claims (20)

1. As a method for manufacturing a first element, A step of providing a first genome layer; Step of providing a first conductive structure and a second conductive structure - each of the first conductive structure and the second conductive structure is at least partially embedded within the first dielectric layer, and the width of the first conductive structure is greater than the width of the second conductive structure -; Step of providing a first portion of a first embedded layer on the first conductive structure - the first portion of the first embedded layer is at least partially embedded within the first conductive structure -; and A method for manufacturing a first device, comprising the step of planarizing the first device to form a first bonding surface— wherein the first dielectric layer, the first conductive structure and the second conductive structure, and the first embedded layer are exposed at the first bonding surface.
2. In Article 1, A method for manufacturing a first element, further comprising the step of providing a second portion of the first embedded layer on the second conductive structure, wherein the second portion of the first embedded layer is at least partially embedded within the second conductive structure.
3. In Article 2, A method for manufacturing a first element, wherein the volume of the first part is larger than the volume of the second part.
4. In Article 1, A method for manufacturing a first element, wherein the buried layer comprises a silicon-containing material.
5. In Article 4, The above silicon-containing material comprises SiC, SiC/ SiO2 , SiN/ SiO2 , or silicide, in a method.
6. In Article 1, A method for manufacturing a first element, wherein the buried layer comprises a conductive material different from the material of the first conductive structure or the second conductive feature.
7. In Article 1, A method for manufacturing a first element, wherein at least a portion of the first portion of the first buried layer is in contact with a portion of the first dielectric layer.
8. In Article 1, A method for manufacturing a first element, wherein each of the first conductive structure and the second conductive structure comprises a barrier layer comprising tantalum, titanium, or cobalt.
9. In Article 1, A method for manufacturing a first element, further comprising the step of preparing the first bonding surface of the first element for direct bonding.
10. As a method for manufacturing a bonded structure, Step of providing the first element of claim 1; Step of providing a second device comprising a second dielectric layer, and a third conductive feature and a fourth conductive feature at least partially embedded within the second dielectric layer—the second device having a second junction surface, wherein the second dielectric layer and the third conductive feature and the fourth conductive feature are exposed at the second junction surface—; and The method comprises the step of directly bonding the first bonding surface of the first element to the second bonding surface of the second element—wherein the first dielectric layer is bonded at least partially to the second dielectric layer without an interposed adhesive, and the first conductive structure and the second conductive structure are bonded at least partially to the third conductive structure and the fourth conductive structure, respectively, without an interposed adhesive. A method for manufacturing a bonded structure in which the first buried layer is partially disposed between the first conductive structure and the third conductive structure.
11. In Article 10, A method for manufacturing a bonded structure, wherein the first portion of the first buried layer includes an air gap.
12. In Article 10, A method for manufacturing a bonded structure in which the second conductive structure and the fourth conductive structure are joined to each other without any part of the layer buried between them.
13. As a method of forming a combined structure, A step of providing a first device including a first dielectric layer; A step of forming a first conductive structure comprising a conductive material—the first conductive structure is partially and conformally disposed within a first cavity formed in the first dielectric layer to form a first opening smaller than the first cavity—; A step of forming a second conductive structure comprising the above conductive material - the second conductive structure is partially and conformally disposed within a second cavity formed in the first dielectric layer to form a second opening smaller than the second cavity -; A step of at least partially coating the surfaces of the first conductive structure and the second conductive structure with a material different from the conductive material—wherein the width of the first conductive structure is greater than the width of the second conductive structure, and the first opening is larger than the second opening—; A step of providing a second device comprising a second dielectric layer, a third conductive structure and a fourth conductive structure respectively embedded within the second dielectric layer; and The method includes the step of directly joining the first element to the second element, A method for forming a bonded structure, wherein the first dielectric layer and the second dielectric layer are directly bonded to each other without an interposed adhesive, the first conductive structure and the third conductive structure are bonded to each other by contacting each other with the first opening in between, and the second conductive structure and the fourth conductive structure are bonded to each other by contacting each other with the second opening in between.
14. In Article 13, A method for forming a combined structure in which the cross-sectional width of the first opening is greater than three times the thickness of the first conductive structure.
15. In Article 14, A method for forming a combined structure in which the depth of the first opening is greater than the cross-sectional width of the first opening.
16. In Article 13, A method for forming a bonded structure, wherein the material coated on the surface of the first conductive structure and the second conductive structure comprises a silicon-containing dielectric material.
17. In Article 13, A method for forming a bonded structure, wherein the material coated on the surface of the first conductive structure and the second conductive structure comprises tungsten, nickel, titanium, or cobalt.
18. In Article 13, A method for forming a combined structure in which the first conductive structure is a through-hole and the first opening is a through-hole.
19. In Article 13, A method for forming a combined structure, wherein the thickness of the material coated on the surface of the first conductive structure and the second conductive structure is thinner than the thickness of the first conductive structure or the second conductive structure.
20. In Article 13, A method for forming a combined structure in which the thickness of the first conductive structure is thinner than the thickness of the second conductive structure.

Description

Interconnect Structures Priority claims and cross-references of related applications This application claims the benefit of U.S. non-application No. 16/657,696 filed on October 18, 2019, and also claims the benefit of priority of U.S. provisional application No. 62/748,653 filed on October 22, 2018, and U.S. provisional application No. 62/902,207 filed on September 18, 2019, under 35 U.S.C. §119(e)(1), the two applications are incorporated herein in their entirety by reference. The following description relates to integrated circuits (ICs). More specifically, the following description relates to the manufacture of IC dies and wafers. Microelectronic devices often comprise a thin slab of semiconductor material, such as silicon or gallium arsenide, commonly referred to as a semiconductor wafer. The wafer may be formed to contain multiple integrated chips or dies embedded on the surface of the wafer and/or partially within the wafer. Dies separated from the wafer are typically provided as individual prepackaged units. In some package designs, the die is mounted on a substrate or chip carrier, which is mounted on a circuit panel such as a printed circuit board (PCB). For example, many dies are provided in packages suitable for surface mounting. Packaged semiconductor dies may be provided in a “stacked” arrangement, wherein one package is provided, for example, on a circuit board or other carrier, and another package is mounted on the top surface of the first package. By these arrangements, multiple different dies or devices can be mounted within a single footprint on a circuit board, and high-speed operation can be further facilitated by providing short interconnections between the packages. In many cases, this interconnection distance may be only slightly greater than the thickness of the die itself. For interconnections achieved within the stack of die packages, interconnection structures for mechanical and electrical connections may be provided on both sides (for example, the surface) of each die package (excluding the top package). Additionally, dies or wafers may be stacked in a three-dimensional array as part of various microelectronic packaging methods. This may include stacking one or more layers of dies, devices, and/or wafers on a larger base die, device, wafer, substrate, etc., stacking multiple dies or wafers in a vertical or horizontal array, and various combinations of both. Dies or wafers may be bonded in a stacked array using various bonding technologies, including direct dielectric bonding, non-bonding technologies (e.g., ZiBond®), or hybrid bonding technologies (e.g., DBI®), both of which are available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.) and Xperi. This bonding involves a spontaneous process that occurs under ambient conditions when two prepared surfaces come into contact (see, for example, U.S. Patents No. 6,864,585 and No. 7,485,968, the entirety of which is incorporated herein). When bonding stacked dies using direct bonding technology, it is generally desirable for the surface of the dies to be bonded to be very flat and smooth. For example, typically, the surface topography must have very little variation (i.e., nanometer-scale variation) so that the surfaces can be closely bonded to form a permanent bond. One or more bonding surfaces of the die or wafer are typically flattened using chemical-mechanical polishing (CMP) or the like to achieve the very flat and smooth surface required for bonding. Each bonding surface of the die or wafer to be bonded (which may include silicon or other suitable materials) often includes a conductive interconnect structure (which may be metal) embedded within an inorganic dielectric layer (e.g., oxide, nitride, oxynitride, oxycarbide, carbide, carbonitride, diamond, diamond-like material, glass, ceramic, glass-ceramic, etc.) on the bonding surface. Conductive interconnect structures can be formed by (for example) a damascene technique and may include structures of various widths and sizes. The conductive interconnect structures may be positioned or aligned on the bonding surface so that these conductive interconnect structures from each die surface are bonded during the bonding operation. The bonded interconnect structures form continuous conductive interconnects (for signal, power, heat transfer, mechanical stability, etc.) between stacked dies or wafers. The exposed surface of the embedded conductive interconnect structure may be planarized together with or separately from the bonding surface of the die or wafer. The profile and/or topography of the exposed surface of the conductive interconnect structure may be important not only for forming a reliable continuous conductive interconnect between the die or wafer but also for forming a reliable dielectric-dielectric junction between the die or wafer. A detailed explanation is provided with reference to the attached drawings. In the drawings, the leftmost digit of a reference