Search

KR-20260064785-A - SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

KR20260064785AKR 20260064785 AKR20260064785 AKR 20260064785AKR-20260064785-A

Abstract

A semiconductor package with reduced size and improved performance and a method for manufacturing the same are provided. The semiconductor package comprises a base substrate having a first surface and a second surface opposite in a first direction, a first connection pad disposed on the first surface, a first solder resist layer disposed on the first surface and covering at least a portion of the side and top surfaces of the first connection pad and defining a first opening region on the first connection pad, a second solder resist layer covering at least a portion of the top surface of the first solder resist layer and defining a second opening region on the first connection pad and the first solder resist layer, and a first solder ball disposed within the first opening region and the second opening region and in contact with the first connection pad, wherein in a second direction parallel to the first surface, the first width of the first opening region is smaller than the second width of the second opening region.

Inventors

  • 유도혁

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260508
Application Date
20241029

Claims (10)

  1. A base substrate including a first surface and a second surface opposite in a first direction; A first connection pad disposed on the first surface above; A first solder resist layer disposed on the first surface, covering at least a portion of the side and upper surfaces of the first connection pad, and defining a first opening region on the first connection pad; A second solder resist layer covering at least a portion of the upper surface of the first solder resist layer and defining a second opening region on the first connection pad and the first solder resist layer; A first solder ball disposed within the first opening region and the second opening region and in contact with the first connection pad, comprising: A semiconductor package in which, in a second direction parallel to the first surface, the first width of the first opening region is smaller than the second width of the second opening region.
  2. In Article 1, A semiconductor chip disposed on the first solder ball, in contact with the first solder ball, and connected to the first connection pad, and A semiconductor package comprising an underfill film disposed between the semiconductor chip and the second solder resist layer and surrounding the first solder ball.
  3. In Article 1, A semiconductor package in which the height from the upper surface of the first connection pad to the upper surface of the first solder resist layer is smaller than the height from the upper surface of the first solder resist layer to the upper surface of the second solder resist layer.
  4. In Article 1, A semiconductor package, wherein the height from the upper surface of the first solder resist layer to the upper surface of the second solder resist layer is at least twice the height from the upper surface of the first connection pad to the upper surface of the first solder resist layer.
  5. In Article 1, A semiconductor package in which the third width in the second direction of the first solder ball is larger than the first width of the first opening region.
  6. In Article 1, A semiconductor package in which the first angle formed by the side of the first solder resist layer with the upper surface of the first connection pad and the second angle formed by the side of the second solder resist layer with the upper surface of the first solder resist layer are different.
  7. In Article 1, A second connection pad disposed on the second surface, and A third solder resist layer disposed on the second surface, covering at least a portion of the side and bottom surfaces of the second connection pad, and defining a third opening region on the second connection pad, and A semiconductor package further comprising a fourth solder resist layer covering at least a portion of the bottom surface of the third solder resist layer and defining a fourth opening region on the second connection pad and the third solder resist layer.
  8. In Article 7, A second solder ball disposed within the third opening region and the fourth opening region and in contact with the second connection pad, and The circuit board further comprises a circuit board disposed on the second solder ball, in contact with the second solder ball, and connected to the second connection pad. A semiconductor package in which, in the second direction above, the third width of the third opening region is smaller than the fourth width of the fourth opening region.
  9. A base substrate including a first surface and a second surface opposite in a first direction; A first connection pad disposed on the first surface above; A first solder resist layer disposed on the first surface, covering at least a portion of the side and upper surfaces of the first connection pad, and defining a first opening region on the first connection pad; A second solder resist layer covering at least a portion of the upper surface of the first solder resist layer and defining a second opening region on the first connection pad and the first solder resist layer; A first solder ball disposed within the first opening region and the second opening region and in contact with the first connection pad; A semiconductor chip disposed on the first solder ball, in contact with the first solder ball, and connected to the first connection pad; and The semiconductor chip and the second solder resist layer are disposed between each other and include an underfill film that surrounds the first solder ball. In a second direction parallel to the first surface, the first width of the first opening area is smaller than the second width of the second opening area, and A semiconductor package in which the first solder ball protrudes in the first direction above the second solder resist layer.
  10. A base substrate comprising a first surface and a second surface opposite in a first direction is provided, and A connection pad disposed on the first surface is formed, and A first solder resist layer is formed that is disposed on the first surface and covers at least a portion of the side and upper surfaces of the connection pad. A second solder resist layer is formed covering at least a portion of the upper surface of the first solder resist layer, and A semiconductor chip connected to the above-mentioned connection pad is mounted on a first surface, comprising: The first solder resist layer defines a first opening region on the connection pad, and The second solder resist layer defines a second opening region on the connection pad and the first solder resist layer, and The semiconductor chip comprises a first solder ball in contact with the connection pad within the first opening region and the second opening region, and A method for manufacturing a semiconductor package in which, in a second direction parallel to the first surface, the first width of the first opening region is smaller than the second width of the second opening region.

Description

Semiconductor Package and Method for Fabricating the Same The present invention relates to a semiconductor device and an electronic system including the same. More specifically, the present invention relates to a semiconductor device including memory cells arranged in three dimensions and an electronic system including the same. Recently, as semiconductor device chip sizes have decreased and the number of I/O terminals has increased due to the miniaturization of process technology and the diversification of functions, electrode pad pitches are becoming increasingly finer; in response, research and development on packaging technology are continuously being carried out. FIG. 1 is a schematic layout diagram for illustrating a semiconductor package according to some embodiments of the present invention. Figure 2 is a schematic cross-sectional view taken along A-A of Figure 1. Figures 3 to 6 are various enlarged views to explain the R1 region of Figure 2. FIGS. 7 and FIGS. 8 are drawings for illustrating a semiconductor package according to some embodiments of the present invention. FIGS. 9 and FIGS. 10 are drawings for illustrating a semiconductor package according to some embodiments of the present invention. FIGS. 11 and FIGS. 12 are drawings for illustrating a semiconductor package according to some embodiments of the present invention. FIG. 13 is a schematic cross-sectional view illustrating a semiconductor package according to some embodiments of the present invention. FIGS. 14 to 22 are intermediate step drawings for explaining a method for manufacturing a semiconductor package according to some embodiments of the present invention. Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. In this specification, although terms such as first, second, upper, and lower are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Accordingly, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention. Furthermore, it is understood that the lower element or component mentioned below may be the upper element or component within the technical scope of the present invention. Hereinafter, a semiconductor package according to exemplary embodiments is described with reference to FIGS. 1 to 13. FIG. 1 is a schematic layout diagram for illustrating a semiconductor package according to some embodiments of the present invention. FIG. 2 is a schematic cross-sectional view taken along A-A of FIG. 1. FIG. 3 to 6 are various enlarged views for illustrating the R1 region of FIG. 2. A semiconductor package according to some embodiments of the present invention may be a package included in a package-in-package (PIP) or a package-on-package (POP). Referring to FIGS. 1 to 6, a semiconductor package according to some embodiments of the present invention may include a circuit board (50), a chip board (100), and a semiconductor chip (200). A chip substrate (100) and a semiconductor chip (200) can be stacked in a third direction (Z) on a circuit board (50). A semiconductor chip (200) can be stacked in a third direction (Z) on a chip substrate (100). That is, a chip substrate (100) can be placed between the circuit board (50) and the semiconductor chip (200). The chip substrate (100) can electrically connect the circuit board (50) and the semiconductor chip (200). In this specification, the first direction (X) and the second direction (Y) may intersect with the third direction (Z), and the first direction (X) and the second direction (Y) may intersect each other. For example, the first direction (X), the second direction (Y), and the third direction (Z) may be substantially perpendicular to each other. The circuit board (50) may be a substrate for a package. The circuit board (50) may be a printed circuit board (PCB). The circuit board (50) may be mounted on the main board of an electronic device, etc. Although not illustrated, the circuit board (50) may be mounted on the main board of the electronic device, etc. through a connecting member. The connecting member may be, for example, in the shape of a solder ball. The circuit board (50) may include a package connection pad (55). The package connection pad (55) may be placed on the upper surface of the circuit board (50). Here, the upper surface may refer to a surface facing the chip board (100) to be described later. The package connection pad (55) may include a conductive material, for example, a metal material. The chip substrate (100) may include a base substrate (110), a conductive pattern (115), a lower passivation film (120), an upper passivatio