KR-20260064839-A - Semiconductor device, electronic apparatus having the same and method of manufacturing the same

Abstract

A semiconductor device, an electronic device, and a method for manufacturing the same are disclosed. The disclosed semiconductor device comprises: a substrate; an oxide semiconductor layer provided on the substrate; a first electrode provided on the oxide semiconductor layer; a second electrode provided on the oxide semiconductor layer spaced apart from the first electrode; a first layer, a second layer, and a third layer provided in at least one of the space between the oxide semiconductor layer and the first electrode and the space between the oxide semiconductor layer and the second electrode; wherein the second layer comprises at least one of tantalum oxide, niobium oxide, strontium oxide, and aluminum oxide.

Inventors

• 정규호
• 김정균
• 김상욱
• 양지은

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20241029

Claims (20)

1. Substrate; An oxide semiconductor layer provided on the above substrate; A first electrode provided in the oxide semiconductor layer; A second electrode provided on the oxide semiconductor layer spaced apart from the first electrode; A first layer, a second layer, and a third layer provided in at least one of the space between the oxide semiconductor layer and the first electrode and the space between the oxide semiconductor layer and the second electrode; A gate insulating layer provided in the oxide semiconductor layer; and Includes a gate electrode provided in the gate insulating layer; The first layer is an indium-containing metal oxide layer comprising at least one of the metals included in the first electrode or the second electrode, and The second layer comprises at least one of tantalum oxide, niobium oxide, strontium oxide, and aluminum oxide, and A semiconductor device in which the third layer comprises indium oxide or indium tin oxide.
2. In Article 1, A semiconductor device wherein the first electrode and the second electrode comprise at least one of W, TiN, Mo, MoN, Ru, and TiSiN.
3. In Article 1, A semiconductor device wherein the first layer comprises at least one of indium-containing TiO2 , indium-containing WOx , indium-containing MoOx , and indium-containing RuO.
4. In Article 1, A semiconductor device having a second layer having a thickness greater than 0 and less than 2 nm.
5. In Article 1, A semiconductor device in which the first electrode and the second electrode are spaced apart in a direction perpendicular to the substrate.
6. In Article 1, A semiconductor device in which the oxide semiconductor layer is an oxide comprising at least one of indium (In), gallium (Ga), zinc (Zn), tungsten (W), tin (Sn), and hafnium (Hf).
7. In Article 1, A semiconductor device having the gate electrode configured to surround the oxide semiconductor layer.
8. In Article 1, A semiconductor device wherein the oxide semiconductor layer, the gate insulating layer, and the gate electrode are each arranged such that their longitudinal directions are perpendicular to the substrate, and the oxide semiconductor layer, the gate insulating layer, and the gate electrode are arranged in a horizontal direction relative to the substrate.
9. In Article 1, A semiconductor device having the above oxide semiconductor layer having a U-shaped cross-section.
10. In Article 1, The oxide semiconductor layer comprises a first oxide semiconductor layer having an L shape arranged such that its longitudinal direction is perpendicular to the substrate, and a second oxide semiconductor layer arranged symmetrically with respect to the first oxide semiconductor layer with respect to the perpendicular direction. A semiconductor device comprising a first gate electrode arranged such that the long direction of the gate electrode is in the vertical direction, and a second gate electrode arranged symmetrically with respect to the first gate electrode with respect to the vertical direction.
11. In Article 1, A semiconductor device having the first electrode, first layer, second layer, third layer, and oxide semiconductor layer having the same width.
12. semiconductor device; It includes a capacitor electrically connected to the above semiconductor device, and The above semiconductor device, Substrate; An oxide semiconductor layer provided on the above substrate; A first electrode provided in the oxide semiconductor layer; A second electrode provided on the oxide semiconductor layer spaced apart from the first electrode; A first layer, a second layer, and a third layer provided in at least one of the space between the oxide semiconductor layer and the first electrode and the space between the oxide semiconductor layer and the second electrode; A gate insulating layer provided in the oxide semiconductor layer; and Includes a gate electrode provided in the gate insulating layer; The first layer is an indium-containing metal oxide layer comprising at least one of the metals included in the first electrode or the second electrode, and The second layer comprises at least one of tantalum oxide, niobium oxide, strontium oxide, and aluminum oxide, and An electronic device in which the third layer comprises indium oxide or indium tin oxide.
13. In Article 12, An electronic device wherein the first electrode and the second electrode comprise at least one of W, TiN, Mo, MoN, Ru, and TiSiN.
14. In Article 12, An electronic device wherein the first layer comprises at least one of indium-containing TiO2 , indium-containing WOx , indium-containing MoOx , and indium-containing RuO.
15. In Article 12, An electronic device having a second layer having a thickness greater than 0 and less than 2 nm.
16. In Article 12, An electronic device in which the first electrode and the second electrode are spaced apart in a direction perpendicular to the substrate.
17. In Article 12, The first electrode is composed of a plurality of bit lines extended along a first direction, and The oxide semiconductor layer is electrically connected to each of the plurality of bit lines and is arranged to extend along a second direction that intersects perpendicularly to the first direction, and An electronic device comprising a plurality of word lines (WL) that extend to intersect the plurality of oxide semiconductor layers along a third direction perpendicular to the first direction and the second direction, wherein the gate electrode is formed.
18. Step of forming a first electrode on a substrate; A step of oxidizing the interface of the first electrode to form a first layer; A step of forming a second layer on the first layer; A step of forming a third layer on the second layer; A step of doping indium into the first layer by diffusing indium from the third layer to the first layer through heat treatment; The method includes the step of forming an oxide semiconductor layer on the third layer; The first layer is an indium metal oxide layer comprising at least one of the metals included in the first electrode, and The second layer comprises at least one of tantalum oxide, niobium oxide, strontium oxide, and aluminum oxide, and A method for manufacturing a semiconductor device, wherein the third layer comprises indium oxide or indium tin oxide.
19. In Article 18, A method for manufacturing a semiconductor device, wherein the first layer comprises at least one of indium-containing TiO2 , indium-containing WOx , indium-containing MoOx , and indium-containing RuO.
20. In Article 18, A method for manufacturing a semiconductor device, wherein the second layer has a thickness greater than 0 and less than 2 nm.

Description

Semiconductor device, electronic apparatus having the same and method of manufacturing the same An exemplary embodiment relates to a semiconductor device including a layer capable of reducing contact resistance between an electrode and an oxide semiconductor layer, an electronic device including the semiconductor device, and a method for manufacturing the semiconductor device. Transistors are semiconductor devices that perform the role of electrical switching and are employed in various integrated circuits, including memory, driver ICs, and logic devices. As the integration density of integrated circuits increases, the space occupied by transistors is rapidly shrinking; therefore, research is underway to maintain performance while reducing the size of transistors. One of the critical components of a transistor is the gate electrode. When voltage is applied to the gate electrode, the adjacent channel opens the path for current, and conversely, blocks the current. The performance of a semiconductor depends on how effectively leakage current is reduced and managed at the gate electrode and channel. In a transistor, power efficiency increases as the contact area between the gate electrode, which controls current, and the channel increases. As semiconductor processes become more miniaturized, transistor sizes decrease, and the contact area between the gate electrode and the channel shrinks, leading to problems caused by the short channel effect. Examples include threshold voltage variation, carrier velocity saturation, deterioration of the subthreshold characteristics, and on-current reduction. Accordingly, methods to overcome the short channel effect and effectively reduce the channel length are being sought. FIG. 1 illustrates a semiconductor device according to an exemplary embodiment. FIG. 2 illustrates a semiconductor device according to another exemplary embodiment. FIG. 3 illustrates a semiconductor device according to another exemplary embodiment. Figure 4 illustrates an example in which the oxide semiconductor layer is deformed in the semiconductor device of Figure 3. Figure 5 illustrates an example in which the first layer, second layer, and third layer are deformed in the semiconductor device of Figure 3. FIG. 6 illustrates a semiconductor device according to another exemplary embodiment. Figure 7 illustrates a semiconductor device of a comparative example. Figure 8 shows the VI graph of a semiconductor device according to an exemplary embodiment and a comparative example. FIG. 9 shows VI graphs of an example and a comparative example in which the thickness of the second layer of a semiconductor device according to an exemplary embodiment is configured differently. FIG. 10 illustrates a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment. FIGS. 11 to 22 are drawings for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. FIG. 23 illustrates an example in which a semiconductor device according to an exemplary embodiment is applied to a DRAM. FIG. 24 illustrates an example in which a semiconductor device according to an exemplary embodiment is applied to a vertically stacked memory device. FIG. 25 illustrates an example in which a semiconductor device according to an exemplary embodiment is applied to a different vertically stacked memory device. FIG. 26 is a schematic block diagram of a display driver integrated circuit (display driver IC: DDI) including a semiconductor element according to an exemplary embodiment and a display device having the DDI. FIG. 27 is a circuit diagram of a CMOS inverter including a semiconductor device according to an exemplary embodiment. FIG. 28 is a circuit diagram of a CMOS SRAM device including a semiconductor device according to an exemplary embodiment. FIG. 29 is a circuit diagram of a CMOS NAND circuit including a semiconductor device according to an exemplary embodiment. FIG. 30 is a block diagram of an electronic system including a semiconductor device according to an exemplary embodiment. FIG. 31 is a block diagram of an electronic system including a semiconductor device according to an exemplary embodiment. Hereinafter, semiconductor devices, electronic devices including semiconductor devices, and methods for manufacturing the same according to various embodiments will be described in detail with reference to the attached drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation. Terms such as "first," "second," etc., may be used to describe various components, but the components should not be limited by these terms. The terms are used solely for the purpose of distinguishing one component from another. A singular expression includes a plural expression unless the context clearly indicates otherwise. Furthermore, when a part is