KR-20260064848-A - Semiconductor structure based on multi-face unit structure

KR20260064848AKR 20260064848 AKR20260064848 AKR 20260064848AKR-20260064848-A

Abstract

A semiconductor structure based on a multifaceted unit structure is provided. The semiconductor structure may include a computational structure comprising a first multifaceted structure having a first signal path formed therein and computational chips disposed on the faces of the first multifaceted structure and connected to the first signal path; an interface structure comprising a second multifaceted structure having a second signal path formed therein and interface chips disposed on the faces of the second multifaceted structure and connected to the second signal path; and a multifaceted connection structure having a third signal path formed therein and connecting the third signal path to the first signal path and the second signal path by contacting a first connection face among the faces of the first multifaceted structure and a second connection face among the faces of the second multifaceted structure.

Inventors

홍혁기
박기태
강준성
김미경
김종한
신창우
이탁형
정병수
주아네스

Assignees

삼성전자주식회사

Dates

Publication Date: 20260508
Application Date: 20241029

Claims (20)

In semiconductor structures, A computational structure comprising a first multi-face structure having a first signal path formed therein and computational chips disposed on the faces of the first multi-face structure and connected to the first signal path; An interface structure comprising a second polyhedral structure having a second signal path formed therein and interface chips disposed on the faces of the second polyhedral structure and connected to the second signal path; and A multi-face connection structure having a third signal path formed internally, and connecting the third signal path to the first signal path and the second signal path by contacting a first connecting surface among the faces of the first multi-face structure and a second connecting surface among the faces of the second multi-face structure. A semiconductor structure including
In paragraph 1, Operational structures including the above operational structure, interface structures including the above interface structure, and multifaceted connection structures including the above multifaceted connection structure form a repetitive three-dimensional pattern in the semiconductor structure. Semiconductor structure.
In paragraph 2, The above repetitive three-dimensional pattern is Sub-patterns including the above operation structures, the above interface structures, and the above multi-faceted connection structures in different combination ratios, Semiconductor structure.
In paragraph 2, The above repetitive three-dimensional pattern is A first sub-pattern in which a first interface structure among the interface structures is connected to one of the faces of a first polyhedral connection structure among the polyhedral connection structures, and a first operation structure among the operation structures is connected to the remaining faces of the first polyhedral connection structure excluding the one mentioned above; A second sub-pattern in which the second interface structures among the interface structures are connected to two of the faces of the second polyhedral connection structure among the polyhedral connection structures, and the second operation structures among the operation structures are connected to the remaining faces of the second polyhedral connection structure excluding the two faces; A third sub-pattern in which the third interface structures among the interface structures are connected to all faces of the third polyhedral connection structure among the polyhedral connection structures; and A fourth sub-pattern in which a fourth operation structure among the operation structures is connected to one of the faces of a fourth polyhedral connection structure among the above polyhedral connection structures, and a fourth interface structure among the interface structures is connected to the remaining faces of the fourth polyhedral connection structure excluding the one mentioned above. A semiconductor structure comprising one or more of
In paragraph 2, One or more of the above operation structures, the above interface structures, and the above multifaceted connection structures are connected to a substrate, Semiconductor structure.
In paragraph 2, The first structure among the above operation structures, the above interface structures, and the above multifaceted connection structures is connected to a first substrate region, and Among the above operation structures, the above interface structures, and the above multifaceted connection structures, the second structure is connected to the second substrate region, and Input data is input through the above-mentioned first structure, and Output data is output through the above second structure, Semiconductor structure.
In paragraph 2, A cooling tunnel is provided in the space between the above operation structures, the above interface structures, and the above multifaceted connection structures, Semiconductor structure.
In paragraph 1, The above computation chips are Connected to the first connection surface through the first signal path, and The above interface chips are Connected to the second connection surface through the second signal path, As the above-described multifaceted connection structure contacts the first connection surface and the second connection surface, the computation chips and the interface chips are connected to each other through the first signal path, the second signal path, and the third signal path. Semiconductor structure.
In paragraph 1, One or more of the first signal path, the second signal path, and the third signal path are including one or more wired paths, wireless paths, and optical paths, Semiconductor structure.
In paragraph 1, The above computation chips are Performs one or more computational and memory functions, The above interface chips are Performing one or more communication and power functions, Semiconductor structure.
In paragraph 1, The first polyhedral structure, the second polyhedral structure, and the polyhedral connection structure are in the shape of a cube. Semiconductor structure.
In semiconductor packaging, Substrate; and A semiconductor structure including operation structures, interface structures, and multi-sided connection structures Includes, One or more of the above operation structures, the above interface structures, and the above multifaceted connection structures are connected to a substrate, and The above operation structures, the above interface structures, and the above multi-faceted connection structures form a repetitive three-dimensional pattern, and The operation structure of the above operation structures is It includes a first polyhedral structure and computation chips disposed on the faces of the first polyhedral structure, and The interface structure of the above interface structures is It includes a second polyhedral structure and interface chips disposed on the faces of the second polyhedral structure, and The polyhedral connection structure of the above polyhedral connection structures is Connected to the operation structure and the interface structure through the first connecting surface among the faces of the first polyhedral structure and the second connecting surface among the faces of the second polyhedral structure, Semiconductor package.
In Paragraph 12, The above repetitive three-dimensional pattern is Sub-patterns including the above operation structures, the above interface structures, and the above multi-faceted connection structures in different combination ratios, Semiconductor package.
In Paragraph 12, The above repetitive three-dimensional pattern is A first sub-pattern in which a first interface structure among the interface structures is connected to one of the faces of a first polyhedral connection structure among the polyhedral connection structures, and a first operation structure among the operation structures is connected to the remaining faces of the first polyhedral connection structure excluding the one mentioned above; A second sub-pattern in which the second interface structures among the interface structures are connected to two of the faces of the second polyhedral connection structure among the polyhedral connection structures, and the second operation structures among the operation structures are connected to the remaining faces of the second polyhedral connection structure excluding the two faces; A third sub-pattern in which the third interface structures among the interface structures are connected to all faces of the third polyhedral connection structure among the polyhedral connection structures; and A fourth sub-pattern in which a fourth operation structure among the operation structures is connected to one of the faces of a fourth polyhedral connection structure among the above polyhedral connection structures, and a fourth interface structure among the interface structures is connected to the remaining faces of the fourth polyhedral connection structure excluding the one mentioned above. A semiconductor package comprising one or more of
In Paragraph 12, The first structure among the above operation structures, the above interface structures, and the above multifaceted connection structures is connected to a first substrate region, and Among the above operation structures, the above interface structures, and the above multifaceted connection structures, the second structure is connected to the second substrate region, and Input data is input through the above-mentioned first structure, and Output data is output through the above second structure, Semiconductor package.
In Paragraph 12, A cooling tunnel is provided in the space between the above operation structures, the above interface structures, and the above multifaceted connection structures, Semiconductor package.
In Paragraph 12, A first signal path connected to the computation chips is formed inside the first polyhedral structure, and A second signal path connected to the interface chips is formed inside the second polyhedral structure, and A third signal path is formed inside the above-mentioned multifaceted connection structure, Semiconductor package.
In Paragraph 17, The above computation chips are Connected to the first connection surface through the first signal path, and The above interface chips are Connected to the second connection surface through the second signal path, As the above-described multifaceted connection structure contacts the first connection surface and the second connection surface, the computation chips and the interface chips are connected to each other through the first signal path, the second signal path, and the third signal path. Semiconductor package.
In Paragraph 17, One or more of the first signal path, the second signal path, and the third signal path are including one or more wired paths, wireless paths, and optical paths, Semiconductor package.
In semiconductor structures, A first computational structure comprising a first polyhedral structure having a first signal path formed therein and computational chips disposed on the faces of the first polyhedral structure and connected to the first signal path; A second computational structure comprising a second polyhedral structure having a second signal path formed therein and computational chips disposed on the faces of the second polyhedral structure and connected to the second signal path; A multifaceted connection structure having a third signal path formed internally, and contacting a first connecting surface among the faces of the first multifaceted structure and a second connecting surface among the faces of the second multifaceted structure to connect the third signal path to the first signal path and the second signal path. A semiconductor structure including

Description

Semiconductor structure based on multi-face unit structure The following embodiments relate to semiconductor structures based on a polyhedral unit structure. The integration density of integrated circuits (e.g., computational circuits, memory circuits, etc.) is continuously increasing. Recently, due to the advancement of artificial intelligence (AI), AI-oriented integrated circuits are being developed. For instance, computational circuits for data-intensive AI computations such as deep learning (e.g., AI accelerators) and high-performance memory supporting these circuits (e.g., HBM (high bandwidth memory)) have emerged. For instance, these computational circuits and high-performance memory can be utilized on a large scale in data centers. These computational circuits and high-performance memory can deliver higher performance than traditional processors and memory in training AI models or performing inference using AI models. FIG. 1 is a drawing exemplarily showing a fractal structure and a general planar structure of one embodiment. FIG. 2 is an exemplary drawing illustrating the expandability of a fractal structure according to one embodiment. FIG. 3 is a drawing exemplifying a fractal structure, a general planar structure, a general stacked structure, and a general three-dimensional structure of one embodiment. FIG. 4 is a drawing that exemplarily illustrates the configuration and structure of a unit structure according to one embodiment. FIG. 5 is a diagram exemplarily illustrating a production process of multifaceted structures according to one embodiment. FIG. 6 is a diagram exemplarily illustrating a production process of a unit structure according to one embodiment. FIG. 7 is a diagram illustrating an exemplary semiconductor structure based on various types of unit structures according to one embodiment. FIGS. 8 and 9 are drawings illustrating the configuration and structure of a semiconductor package according to one embodiment. FIG. 10 is a drawing exemplarily showing a cooling tunnel according to one embodiment. FIGS. 11 and FIGS. 12 are drawings illustrating exemplary sub-patterns of a repetitive three-dimensional pattern according to one embodiment. FIG. 13 is a diagram exemplarily illustrating multiple connections between a semiconductor structure and a substrate according to one embodiment. FIG. 14 is a diagram exemplarily showing semiconductor structures disposed on both sides of a substrate according to one embodiment. FIG. 15 is a drawing exemplarily showing a semiconductor structure connected to a plurality of substrate regions according to one embodiment. FIG. 16 is a drawing exemplarily illustrating a unit structure including an optical signal path according to one embodiment. FIG. 17 is a drawing illustrating the configuration of an electronic device according to one embodiment. Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Accordingly, actual implementations are not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or substitutions included in the technical concept described by the embodiments. Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component. When it is stated that a component is "connected" to another component, it should be understood that it may be directly connected to or coupled with that other component, or that there may be other components in between. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, terms such as "comprising" or "having" are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. In this specification, each of the phrases such as “at least one of A or B” and “at least one of A, B, or C” may include any one of the items listed together with the corresponding phrase, or all possible combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification. Hereinafter, embodiments will be described in de