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KR-20260064867-A - GATE DRIVER, DISPLAY APPARATUS HAVING THE SAME AND ELECTRONIC APPARATUS HAVING THE SAME

KR20260064867AKR 20260064867 AKR20260064867 AKR 20260064867AKR-20260064867-A

Abstract

The gate drive unit includes a plurality of stages. The stage comprises a first-1 transistor including a control electrode to which a first clock signal is applied, a first electrode to which an input signal is applied, and a second electrode connected to a first intermediate node; a first-2 transistor including a control electrode to which a first clock signal is applied, a first electrode connected to a first intermediate node, and a second electrode connected to a Q node; a second-1 transistor including a control electrode connected to a third control node, a first electrode connected to a first intermediate node, and a second electrode connected to a first control node; a second-2 transistor including a control electrode connected to a third control node, a first electrode to which a second low voltage is applied, and a second electrode connected to a first intermediate node; a third transistor including a control electrode to which a high voltage is applied, a first electrode connected to a first control node, and a second electrode connected to a second control node; a fifth transistor including a control electrode connected to a second control node, a first electrode to which a high voltage is applied, and a second electrode connected to a carry output terminal; and a control electrode connected to a second control node, a first electrode to which a second low voltage is applied, and a component connected to a carry output terminal. It includes a sixth transistor including a second electrode, a control electrode connected to a second control node, a first electrode to which a high voltage is applied, a seventh transistor including a second electrode connected to a gate output terminal, and a control electrode connected to a third control node, a first electrode to which a first low voltage is applied, and a second electrode connected to a gate output terminal.

Inventors

  • 정준기
  • 서영완
  • 안종엽

Assignees

  • 삼성디스플레이 주식회사

Dates

Publication Date
20260508
Application Date
20241030

Claims (20)

  1. It includes multiple stages, The above stage is, A first-1 transistor comprising a control electrode to which a first clock signal is applied, a first electrode to which an input signal is applied, and a second electrode connected to a first intermediate node; A first-2 transistor comprising a control electrode to which the first clock signal is applied, a first electrode connected to the first intermediate node, and a second electrode connected to the Q node; A second-1 transistor comprising a control electrode connected to a third control node, a first electrode connected to the first intermediate node, and a second electrode connected to the first control node; A second-2 transistor comprising a control electrode connected to the third control node, a first electrode to which a second low voltage is applied, and a second electrode connected to the first intermediate node; A third transistor comprising a control electrode to which a high voltage is applied, a first electrode connected to the first control node, and a second electrode connected to the second control node; A fifth transistor comprising a control electrode connected to the second control node, a first electrode to which the high voltage is applied, and a second electrode connected to a carry output terminal; A sixth transistor comprising a control electrode connected to the third control node, a first electrode to which the second low voltage is applied, and a second electrode connected to the carry output terminal; A seventh transistor comprising a control electrode connected to the second control node, a first electrode to which the high voltage is applied, and a second electrode connected to a gate output terminal; and A gate driver comprising an eighth transistor including a control electrode connected to the third control node, a first electrode to which a first low voltage is applied, and a second electrode connected to the gate output terminal.
  2. In paragraph 1, the above stage is, A fourth transistor comprising a control electrode connected to the second control node, a first electrode to which a second clock signal is applied, and a second electrode connected to the second electrode of the first capacitor; and A gate driver further comprising a first electrode connected to the second control node and a first capacitor including the second electrode.
  3. In paragraph 1, the above stage is, A gate driver further comprising a second capacitor including a first electrode connected to the second control node and a second electrode connected to the gate output terminal.
  4. In paragraph 1, the above stage is, A 9-1 transistor comprising a control electrode to which the above high voltage is applied, a first electrode connected to a first node, and a second electrode connected to a 9th intermediate node; A 9-2 transistor comprising a control electrode to which the high voltage is applied, a first electrode connected to the 9th intermediate node, and a second electrode to which the high voltage is applied; and A gate driver further comprising a control electrode connected to the first node, a first electrode to which the high voltage is applied, and a tenth transistor connected to the third control node.
  5. In paragraph 4, the above stage is, A gate driver further comprising a third capacitor including a first electrode connected to the first node and a second electrode connected to the third control node.
  6. In paragraph 5, the above stage is, A 11th transistor comprising a control electrode connected to the first control node, a first electrode to which the first low voltage is applied, and a second electrode connected to the first node; and A gate driver further comprising a 12th transistor including a control electrode connected to the first control node, a first electrode to which the second low voltage is applied, and a second electrode connected to the third control node.
  7. In paragraph 1, the above stage is, A 13-1 transistor comprising a control electrode connected to the first control node, a first electrode to which the high voltage is applied, and a second electrode connected to the 13 intermediate node; and A gate driver further comprising a 13-2 transistor including a control electrode connected to the first control node, a first electrode connected to the 13 intermediate node, and a second electrode connected to the first intermediate node.
  8. In paragraph 1, the above stage is, A 14-1 transistor comprising a control electrode to which a reset signal is applied, a first electrode connected to the first intermediate node, and a second electrode connected to the Q node; and A gate driver further comprising a 14-2 transistor including a control electrode to which the above reset signal is applied, a first electrode to which the above first low voltage is applied, and a second electrode connected to the above first intermediate node.
  9. In claim 1, the plurality of stages includes a first stage, a second stage, a third stage and a fourth stage arranged sequentially, and The carry signal of the first stage is applied to the second stage, and The carry signal of the second stage is applied to the third stage, and The carry signal of the third stage is applied to the fourth stage, and The first clock signal is applied to the first clock terminal of the first stage, and the second clock signal is applied to the second clock terminal of the first stage, and The second clock signal is applied to the first clock terminal of the second stage, and the first clock signal is applied to the second clock terminal of the second stage, and The first clock signal is applied to the first clock terminal of the third stage, and the second clock signal is applied to the second clock terminal of the third stage, and A gate driving unit characterized in that the second clock signal is applied to the first clock terminal of the fourth stage, and the first clock signal is applied to the second clock terminal of the fourth stage.
  10. A gate driving unit according to claim 9, characterized in that the period of the first clock signal is two horizontal intervals, the period of the second clock signal is two horizontal intervals, and the high interval of the pulse of the gate output signal is two horizontal intervals.
  11. A gate driver according to claim 10, characterized in that the high section of the first clock signal does not overlap with the high section of the second clock signal.
  12. In claim 1, the plurality of stages includes a first stage, a second stage, a third stage and a fourth stage arranged sequentially, and The carry signal of the first stage is applied to the third stage, and The carry signal of the second stage is applied to the fourth stage, and The first clock signal is applied to the first clock terminal of the first stage, and the second clock signal is applied to the second clock terminal of the first stage, and A third clock signal is applied to the first clock terminal of the second stage, and a fourth clock signal is applied to the second clock terminal of the second stage, and The second clock signal is applied to the first clock terminal of the third stage, and the first clock signal is applied to the second clock terminal of the third stage, and A gate driver characterized in that the fourth clock signal is applied to the first clock terminal of the fourth stage, and the third clock signal is applied to the second clock terminal of the fourth stage.
  13. A gate driving unit according to claim 12, characterized in that the period of the first clock signal is 4 horizontal intervals, the period of the second clock signal is 4 horizontal intervals, the period of the third clock signal is 4 horizontal intervals, the period of the fourth clock signal is 4 horizontal intervals, and the high interval of the pulse of the gate output signal is 4 horizontal intervals.
  14. In paragraph 13, the high interval of the first clock signal does not overlap with the high interval of the second clock signal, and The high section of the third clock signal overlaps with the high section of the first clock signal, and A gate driver characterized in that the high section of the third clock signal overlaps with the high section of the second clock signal.
  15. An input unit that transmits an input signal to a first control node in response to a first clock signal; A pull-up unit that pulls up the gate output signal to a high voltage in response to the signal of the second control node; A pull-down unit that pulls down the gate output signal to a first low voltage in response to a signal from a third control node; A node separation unit comprising a control electrode to which the above high voltage is applied, a first electrode connected to the first control node, and a second electrode connected to the third control node; A first control node control unit that controls the signal of the first control node in response to the signal of the second control node; and A gate driving unit comprising a third control node control unit that controls the signal of the third control node in response to the signal of the first control node.
  16. A display panel containing pixels; A gate driver that outputs a gate signal to the pixel; and It includes a data driver that outputs a data voltage to the pixel, and The above gate driving unit is, A first-1 transistor comprising a control electrode to which a first clock signal is applied, a first electrode to which an input signal is applied, and a second electrode connected to a first intermediate node; A first-2 transistor comprising a control electrode to which the first clock signal is applied, a first electrode connected to the first intermediate node, and a second electrode connected to the Q node; A second-1 transistor comprising a control electrode connected to a third control node, a first electrode connected to the first intermediate node, and a second electrode connected to the first control node; A second-2 transistor comprising a control electrode connected to the third control node, a first electrode to which a second low voltage is applied, and a second electrode connected to the first intermediate node; A third transistor comprising a control electrode to which a high voltage is applied, a first electrode connected to the first control node, and a second electrode connected to the second control node; A fifth transistor comprising a control electrode connected to the second control node, a first electrode to which the high voltage is applied, and a second electrode connected to a carry output terminal; A sixth transistor comprising a control electrode connected to the second control node, a first electrode to which the second low voltage is applied, and a second electrode connected to the carry output terminal; A seventh transistor comprising a control electrode connected to the second control node, a first electrode to which the high voltage is applied, and a second electrode connected to a gate output terminal; and A display device characterized by including an eighth transistor comprising a control electrode connected to the third control node, a first electrode to which a first low voltage is applied, and a second electrode connected to the gate output terminal.
  17. In Clause 16, the gate driving unit is, A fourth transistor comprising a control electrode connected to the second control node, a first electrode to which a second clock signal is applied, and a second electrode connected to the second electrode of the first capacitor; and A display device characterized by further including a first electrode connected to the second control node and a first capacitor including the second electrode.
  18. In Clause 16, the gate driving unit is, A display device characterized by further including a second capacitor comprising a first electrode connected to the second control node and a second electrode connected to the gate output terminal.
  19. In Clause 16, the gate driving unit is, A 9-1 transistor comprising a control electrode to which the above high voltage is applied, a first electrode connected to a first node, and a second electrode connected to a 9th intermediate node; A 9-2 transistor comprising a control electrode to which the high voltage is applied, a first electrode connected to the 9th intermediate node, and a second electrode to which the high voltage is applied; and A display device characterized by further including a control electrode connected to the first node, a first electrode to which the high voltage is applied, and a tenth transistor connected to the third control node.
  20. A display panel containing pixels; A gate driver that outputs a gate signal to the pixel; A data driving unit that outputs data voltage to the pixel; A driving control unit that controls the gate driving unit and the data driving unit; and It includes a processor that outputs input image data to the above-mentioned drive control unit, and The above gate driving unit is, A first-1 transistor comprising a control electrode to which a first clock signal is applied, a first electrode to which an input signal is applied, and a second electrode connected to a first intermediate node; A first-2 transistor comprising a control electrode to which the first clock signal is applied, a first electrode connected to the first intermediate node, and a second electrode connected to the Q node; A second-1 transistor comprising a control electrode connected to a third control node, a first electrode connected to the first intermediate node, and a second electrode connected to the first control node; A second-2 transistor comprising a control electrode connected to the third control node, a first electrode to which a second low voltage is applied, and a second electrode connected to the first intermediate node; A third transistor comprising a control electrode to which a high voltage is applied, a first electrode connected to the first control node, and a second electrode connected to the second control node; A fifth transistor comprising a control electrode connected to the second control node, a first electrode to which the high voltage is applied, and a second electrode connected to a carry output terminal; A sixth transistor comprising a control electrode connected to the second control node, a first electrode to which the second low voltage is applied, and a second electrode connected to the carry output terminal; A seventh transistor comprising a control electrode connected to the second control node, a first electrode to which the high voltage is applied, and a second electrode connected to a gate output terminal; and An electronic device characterized by including an eighth transistor comprising a control electrode connected to the third control node, a first electrode to which a first low voltage is applied, and a second electrode connected to the gate output terminal.

Description

Gate driver, display apparatus having the same, and electronic apparatus having the same The present invention relates to a gate driver, a display device including the same, and an electronic device including the same, wherein the gate driver capable of reducing power consumption, a display device including the same, and an electronic device including the same. Generally, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver that provides a gate signal to the plurality of gate lines, a data driver that provides a data voltage to the data lines, an emission driver that provides an emission signal to the emission lines, and a driving control unit that controls the gate driver, the data driver, and the emission driver. The display panel and the display panel driver may include a P-type transistor or an N-type transistor. To prevent current leakage, the display panel may be formed solely of N-type transistors. If the display panel is formed solely of N-type transistors and the gate driver integrated on the display panel includes a P-type transistor, the manufacturing process becomes complex, and there is a problem of current leakage occurring in the gate driver. In addition, there is a problem in that the display quality of the display panel deteriorates due to flicker occurring on the display panel caused by the current leakage. When a clock signal is used as the gate output signal of the gate driver, there is a problem in that power consumption increases significantly due to the capacitance of the buffer transistor to which the clock signal is applied. In addition, when including the clock signal used as the gate output signal and the carry clock signal used as the carry signal of the gate driver, the size of the buffer transistor cannot be formed sufficiently large due to spatial constraints, and consequently, there is a problem in that the polling time of the gate output signal becomes long. If the polling time of the above gate output signal is prolonged, the data voltage of another pixel is incorrectly applied to the pixel, causing a problem in which the display quality of the above display panel deteriorates. FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. Figure 2 is a block diagram showing the gate driving unit of Figure 1. Figure 3 is a circuit diagram showing the stage of the gate driving unit of Figure 2. Figure 4 is a timing diagram showing the input signal, node signal, and output signal of the gate driver of Figure 2. FIG. 5 is a block diagram showing a gate driving unit of a display device according to one embodiment of the present invention. FIG. 6 is a timing diagram showing the input signal, node signal, and output signal of the gate driver of FIG. 5. FIG. 7 is a circuit diagram showing the stage of the gate driving unit of a display device according to one embodiment of the present invention. FIG. 8 is a timing diagram showing the input signal, node signal, and output signal of the gate driver of FIG. 7. FIG. 9 is a block diagram showing an electronic device according to one embodiment of the present invention. FIG. 10 is a diagram showing an example in which the electronic device of FIG. 9 is implemented as a smartphone. FIG. 11 is a diagram showing an example in which the electronic device of FIG. 9 is implemented as a monitor. FIG. 12 is a block diagram showing an electronic device according to one embodiment of the present invention. Hereinafter, the present invention will be described in more detail with reference to the attached drawings. FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. Referring to FIG. 1, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), a data driver (500), and an emission driver (600). The above display panel (100) includes a display unit (AA) for displaying an image and a peripheral unit (PA) positioned adjacent to the display unit (AA). The display panel (100) may include a plurality of gate lines (GL), a plurality of data lines (DL), a plurality of emission lines (EL), and a plurality of pixels electrically connected to each of the gate lines (GL), the data lines (DL), and the emission lines (EL). The gate lines (GL) may extend in a first direction (D1), the data lines (DL) may extend in a second direction (D2) that intersects the first direction (D1), and the emission lines (EL) may extend in the first direction (D1). The above-described drive control unit (200) can receive input image data (IMG) and input control signals (CONT) from an external device. For example, the input image data (IMG) may inc