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KR-20260064888-A - DRIVER, DISPLAY DEVICE INCLUDING DRIVER, AND ELECTRONIC DEVICE INCLUDING DRIVER

KR20260064888AKR 20260064888 AKR20260064888 AKR 20260064888AKR-20260064888-A

Abstract

The driving unit includes a first gate emission signal generating unit that generates a first driving signal, a second gate emission signal generating unit that generates a second driving signal of a different type from the first driving signal and has a circuit structure substantially identical to that of the first gate emission signal generating unit, a clock wiring disposed between the first gate emission signal generating unit and the second gate emission signal generating unit and outputs a clock signal, and a first low voltage wiring disposed between the first gate emission signal generating unit and the second gate emission signal generating unit and outputs a first low gate voltage. The first gate emission signal generating unit is connected to the clock wiring and the first low voltage wiring, and the second gate emission signal generating unit is connected to the clock wiring and the first low voltage wiring to which the first gate emission signal generating unit is connected.

Inventors

  • 조재형
  • 이동훈
  • 정민재
  • 김일남
  • 우민규
  • 장재용

Assignees

  • 삼성디스플레이 주식회사

Dates

Publication Date
20260508
Application Date
20241030

Claims (20)

  1. A first gate emission signal generating unit that generates a first driving signal; A second gate emission signal generating unit that generates a second driving signal of a different type from the first driving signal and has a circuit structure substantially identical to the first gate emission signal generating unit; A clock wiring disposed between the first gate emission signal generating unit and the second gate emission signal generating unit and outputting a clock signal; and It includes a first low voltage wiring disposed between the first gate emission signal generating unit and the second gate emission signal generating unit, which outputs a first low gate voltage, and The first gate emission signal generator is connected to the clock wiring and the first low voltage wiring, and The driving unit is characterized in that the second gate emission signal generating unit is connected to the clock wiring and the first low voltage wiring to which the first gate emission signal generating unit is connected.
  2. In Article 1, The above driving unit includes a plurality of stages arranged along one direction, and Each of the above plurality of stages includes the first gate emission signal generation unit and the second gate emission signal generation unit, and A driving unit characterized by the above clock wiring including a first clock wiring connected to stages located in odd rows and a second clock wiring connected to stages located in even rows.
  3. A driving unit according to claim 2, characterized in that the first low voltage wiring is positioned between the first clock wiring and the second clock wiring on a plane.
  4. A driving unit according to claim 2, characterized in that the first low voltage wiring, the first clock wiring, and the second clock wiring are arranged on the same layer.
  5. A driving unit according to claim 2, characterized in that the first low voltage wiring, the first clock wiring, and the second clock wiring are arranged on different layers.
  6. A driving unit according to claim 5, characterized in that the first low voltage wiring overlaps at least partially with the first clock wiring or the second clock wiring on a plane.
  7. A driving unit according to claim 5, characterized in that the first low voltage wiring is positioned below the first clock wiring and the second clock wiring.
  8. A driving unit according to claim 1, wherein the first gate emission signal generating unit and the second gate emission signal generating unit are line-symmetric with respect to the first low voltage wiring.
  9. In claim 1, each of the first gate emission signal generating unit and the second gate emission signal generating unit is, An input block that outputs an input signal to a control node in response to the above clock signal; An inversion block that inverts the voltage of the above control node and outputs it to an inversion control node; A carry signal output block that outputs the first low gate voltage to the carry output node in response to the voltage of the control node and outputs the high gate voltage to the carry output node in response to the voltage of the inversion control node; and A driving unit characterized by including a driving signal output block that outputs a second low gate voltage different from the first low gate voltage to a driving output node in response to the voltage of the control node, and outputs the high gate voltage to the driving output node in response to the voltage of the inversion control node.
  10. A driving unit according to claim 9, characterized in that the second low gate voltage is lower than the first low gate voltage.
  11. A display panel including pixels; and It includes a driving unit that outputs a driving signal to the pixel above, and The above driving unit is, A first gate emission signal generating unit that generates a first driving signal; A second gate emission signal generating unit that generates a second driving signal of a different type from the first driving signal and has a circuit structure substantially identical to the first gate emission signal generating unit; A clock wiring disposed between the first gate emission signal generating unit and the second gate emission signal generating unit and outputting a clock signal; and It includes a first low voltage wiring disposed between the first gate emission signal generating unit and the second gate emission signal generating unit, which outputs a first low gate voltage, and The first gate emission signal generator is connected to the clock wiring and the first low voltage wiring, and A display device characterized in that the second gate emission signal generator is connected to the clock wiring and the first low voltage wiring to which the first gate emission signal generator is connected.
  12. A display device according to claim 11, characterized in that the first low voltage wiring and the clock wiring are disposed on the same layer.
  13. A display device according to claim 11, characterized in that the first low voltage wiring and the clock wiring are disposed on different layers.
  14. A display device according to claim 13, characterized in that the first low voltage wiring overlaps at least partially with the clock wiring on a plane.
  15. In claim 11, the display panel is, Substrate; A pixel active pattern disposed on the above substrate; A pixel gate electrode disposed on the pixel active pattern above; A first pixel output electrode and a second pixel output electrode disposed on the pixel gate electrode; A connecting electrode disposed on the first pixel output electrode and the second pixel output electrode; and A display device characterized by including a light-emitting element disposed on the above-mentioned connecting electrode and emitting light.
  16. A display device according to claim 15, characterized in that the first low voltage wiring, the clock wiring, and the connecting electrode are disposed on the same layer.
  17. In Article 15, The first low voltage wiring, the first pixel output electrode, and the second pixel output electrode are disposed on the same layer as each other, and A display device characterized in that the clock wiring and the connecting electrode are disposed on the same layer.
  18. In claim 15, the pixel active pattern is, A first pixel active pattern comprising a silicon semiconductor material; and A display device characterized by including a second pixel active pattern disposed on the first pixel active pattern and comprising an oxide semiconductor material.
  19. In claim 11, the pixel is, A light-emitting element that emits light; A first pixel transistor that provides a driving current to the light-emitting element; A second pixel transistor that provides a data voltage to the first pixel transistor in response to a write gate signal; A third pixel transistor that diode-connects the first pixel transistor in response to a compensation gate signal; A fourth pixel transistor that provides a first initialization voltage to the gate electrode of the first pixel transistor in response to an initialization gate signal; A fifth pixel transistor that provides a driving voltage to the first pixel transistor in response to an emission signal; A sixth pixel transistor that electrically connects the first pixel transistor and the light-emitting element in response to the emission signal; and A display device characterized by including a seventh pixel transistor that provides a second initialization voltage to the first electrode of the light-emitting element in response to a bias gate signal.
  20. A display device according to claim 19, wherein the pixel further comprises an eighth pixel transistor that provides a bias voltage to the first pixel transistor in response to the bias gate signal.

Description

Driving unit, display device including driving unit, and electronic device including driving unit The present invention relates to a driving unit for driving a display panel. More specifically, the present invention relates to a driving unit for driving a display panel, a display device including the driving unit, and an electronic device including the driving unit. As information technology develops, the importance of display devices, which serve as a medium of connection between users and information, is being highlighted. For example, the use of display devices such as liquid crystal display devices (LCDs), organic light emitting diode (OLED) displays, plasma display panels (PDPs), and quantum dot displays is increasing. A display device may include a display panel and a driving unit for driving the display panel. The display panel may include gate lines, data lines, emission lines, and pixels. The driving unit may include a gate driving unit that provides a gate signal to the gate lines, a data driving unit that provides a data voltage to the data lines, an emission driving unit that provides an emission signal to the emission lines, and a control unit that controls the gate driving unit, the data driving unit, and the emission driving unit. Generally, the display device may include clock wiring and voltage transfer wiring connected to the gate driver and the emission driver. As the number of clock wiring and voltage transfer wiring increases, the integration density of the driver may decrease. FIG. 1 is a plan view showing a display device according to one embodiment of the present invention. Figure 2 is a block diagram showing the display device of Figure 1. FIG. 3a is a circuit diagram showing an example of the circuit structure of a pixel included in the display device of FIG. 1. FIG. 3b is a circuit diagram showing another example of the circuit structure of a pixel included in the display device of FIG. 1. Figure 4 is a cross-sectional view taken along line II' of Figure 1. Figure 5 is a block diagram showing an example of a gate emission drive unit of Figure 2. FIG. 6 is a block diagram showing an example of a stage included in the gate emission drive unit of FIG. 5. FIG. 7 is a circuit diagram showing an example of a stage included in the gate emission driving unit of FIG. 5. Figure 8 is a timing diagram showing an example of the operation of the stage of Figure 7. FIGS. 9 to 21 are layout drawings showing an example of a stage included in the gate emission drive unit of FIG. 5. FIG. 22 is a block diagram showing another example of the gate emission drive unit of FIG. 2. FIG. 23 is a circuit diagram showing an example of a stage included in the gate emission drive unit of FIG. 22. FIGS. 24 to 27 are layout drawings showing an example of a stage included in the gate emission drive unit of FIG. 22. FIG. 28 is a block diagram showing an electronic device according to one embodiment of the present invention. FIG. 29 is a diagram showing an example in which the electronic device of FIG. 28 is implemented as a smartphone. Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted. The present invention may be implemented in various different forms and is not limited to the embodiments described herein. FIG. 1 is a plan view showing a display device according to one embodiment of the present invention. In this specification, a plane may be defined as a first direction (DR1) and a second direction (DR2) that intersects the first direction (DR1). For example, the first direction (DR1) and the second direction (DR2) may be perpendicular to each other. The normal direction of the plane, that is, the thickness direction of the display device (DD), may be a third direction (DR3). In other words, the third direction (DR3) may be perpendicular to the first direction (DR1) and the second direction (DR2), respectively. In this specification, the plan view is a view from the third direction (DR3). Referring to FIG. 1, a display device (DD) according to one embodiment of the present invention may include a display panel (100), a driving chip (D-IC), a first driving unit (DRV1), and a second driving unit (DRV2). The display panel (100) may include a display area (DA) and a non-display area (NDA). The display area (DA) may be defined as an area that displays an image by generating light or controlling the transmittance of light provided from an external light source. The display panel (100) may include pixels (PX) placed in the display area (DA). Each of the pixels (PX) may generate light according to a driving signal. For example, the pixels (PX) may be arranged in a matrix form along a first direction (DR1) and a second direction (DR2). The non-display area (NDA) may be adjacent to the display area (DA). The non-d