KR-20260064918-A - SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Abstract

A semiconductor package according to one embodiment may include: a glass substrate including a glass core including a plurality of through-holes; a plurality of logic dies, each logic die disposed within a corresponding through-hole among the plurality of through-holes; a first redistribution structure on the glass substrate; a bridge die on the first redistribution structure; a plurality of conductive posts on the first redistribution structure; a molding material covering the bridge die and the plurality of conductive posts on the first redistribution structure; a second redistribution structure on the molding material; and a plurality of memory structures on the second redistribution structure.

Inventors

• 조명도
• 김다희
• 고영찬
• 박우석
• 신미소
• 최연찬
• 최재영

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20241030

Claims (10)

1. A glass substrate including a glass core having a plurality of through openings; A plurality of logic dies, each logic die disposed within a corresponding through-opening among the plurality of through-openings; A first redistribution structure on the glass substrate above; Bridge die on the above-mentioned first redistribution structure; A plurality of conductive posts on the first redistribution structure above; A molding material covering the bridge die and the plurality of conductive posts on the first redistribution structure; A second redistribution structure on the above-mentioned molding material; and A plurality of memory structures on the second rewiring structure above A semiconductor package including
2. In paragraph 1, A semiconductor package in which each of the plurality of memory structures is overlapped in a vertical direction with a corresponding logic die among the plurality of logic dies, at least in part.
3. In paragraph 1, The above bridge die is a semiconductor package that routes signals between the plurality of logic dies and the plurality of memory structures.
4. In paragraph 1, The above bridge die is a semiconductor package that routes signals between the plurality of memory structures.
5. In paragraph 1, A semiconductor package in which the first rewiring structure and the second rewiring structure route signals between the plurality of logic dies and the plurality of memory structures.
6. In paragraph 1, The above first rewiring structure is a semiconductor package that routes signals between the plurality of logic dies.
7. In paragraph 1, Each of the above plurality of logic dies is, Logic die base; and Front structure on the above logic die base Includes, A semiconductor package in which each of the above plurality of logic dies is arranged such that the front structure faces the first rewiring structure.
8. In Paragraph 7, Each of the above plurality of logic dies is, A plurality of through silicon vias penetrating the logic die base in the vertical direction and connected to the front structure Includes more, A semiconductor package in which the plurality of through-silicon vias route a signal between the outside and the front structure.
9. In paragraph 1, The above glass substrate is, A plurality of through glass vias penetrating the glass core Includes more, A semiconductor package in which the plurality of through-glass vias and the first rewiring structure route signals between the outside and the plurality of logic dies.
10. In paragraph 1, The above glass substrate is, An organic insulating layer between the glass core and the first redistribution structure, and between the plurality of logic dies and the first redistribution structure; and Wiring lines within the above organic insulating layer A semiconductor package that further includes

Description

Semiconductor Package and Method for Manufacturing the Same The present disclosure relates to a semiconductor package and a method for manufacturing the same. A semiconductor package including a logic die and a High Bandwidth Memory (HBM) that are spaced apart from each other in the horizontal direction may include a bridge die that forms a signal routing path between the logic die and the High Bandwidth Memory (HBM) below the logic die and the High Bandwidth Memory (HBM). However, even with the use of a bridge die, the signal transmission distance between the logic die and the High Bandwidth Memory (HBM) is still long due to the size of the logic die and the High Bandwidth Memory (HBM) itself and due to the spacing between the logic die and the High Bandwidth Memory (HBM), and this long signal transmission distance between the logic die and the High Bandwidth Memory (HBM) can cause problems that degrade the signal transmission speed between the logic die and the High Bandwidth Memory (HBM). In addition, as Artificial Intelligence (AI) and High Performance Computing (HPC) technologies advance, the importance of Power Integrity (PI) and Signal Integrity (SI) in semiconductor packages, including logic dies and High Bandwidth Memory (HBM), has increased. Therefore, it is required to improve the Power Integrity (PI) and Signal Integrity (SI) of semiconductor packages, and to achieve this, it is necessary to optimize the power and signal routing paths within the semiconductor package by reducing the length of the power and signal routing paths and miniaturizing the wiring patterns in which the power and signal routing paths are implemented. FIG. 1 is a cross-sectional view illustrating a semiconductor package of one embodiment. FIG. 2 is a plan view illustrating the top surfaces of various embodiments of the semiconductor package of FIG. 1. FIG. 3 is a plan view showing the top surface of a semiconductor package of one embodiment of FIG. 1. FIG. 4 is a cross-sectional view illustrating a semiconductor package of one embodiment. FIG. 5 is a plan view showing the top surface of a semiconductor package of one embodiment of FIG. 4. FIG. 6 is a cross-sectional view illustrating a semiconductor package of one embodiment. FIG. 7 is a plan view showing the top surface of a semiconductor package of one embodiment of FIG. 6. FIG. 8 is a cross-sectional view illustrating a semiconductor package of one embodiment. FIGS. 9 to 27 are cross-sectional views illustrated to explain a method for manufacturing a semiconductor package of one embodiment of FIG. 1. Hereinafter, embodiments of the present disclosure are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure may be embodied in various different forms and is not limited to the embodiments described herein. In order to clearly explain the present disclosure in the drawings, parts unrelated to the explanation have been omitted, and the same reference numerals have been used throughout the specification for identical or similar components. In addition, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present disclosure is not necessarily limited to what is depicted. Throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected," but also cases where they are "indirectly connected" with other members in between. Furthermore, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Furthermore, when it is said that a part, such as a layer, membrane, region, or plate, is "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. Also, saying that a part is "on" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "on" in the direction opposite to gravity. Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side. Hereinafter, a semiconductor package (100; 100A, 100B, 100C and 100D) of one embodiment and a method for manufacturing the same will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a semiconductor package (100A) of one embodiment. FIG. 1 is a cross-sectional view illustrating semiconductor packages (100A) of one embodiment of FIG. 2 an