KR-20260064923-A - SEMICONDUCTOR DEVICE

KR20260064923AKR 20260064923 AKR20260064923 AKR 20260064923AKR-20260064923-A

Abstract

To solve the above-described problem, one embodiment of the present invention comprises: a semiconductor pattern; a plurality of channel structures arranged spaced apart from each other in one direction on the semiconductor pattern; a plurality of gate structures intersecting each of the plurality of channel structures; source/drain patterns disposed between the plurality of channel structures on the semiconductor pattern; an insulating isolation layer disposed on the lower surface of the semiconductor pattern; a plurality of insulating isolation patterns disposed in regions corresponding to the plurality of gate structures on the lower surface of the insulating isolation layer, each extending toward the plurality of gate structures—the semiconductor pattern is separated into a plurality of pattern regions by the plurality of insulating isolation patterns—; a plurality of contact blocks disposed between the plurality of insulating isolation patterns on the lower surface of the insulating isolation layer; a contact via extending from at least one of the plurality of contact blocks to an adjacent source/drain pattern among the source/drain patterns—a first pattern region through which the contact via penetrates has an impurity concentration higher than the impurity concentration of a second pattern region through which the contact via does not penetrate—; A semiconductor device may be provided comprising: a metal-semiconductor compound layer disposed between the first pattern region and the adjacent source/drain pattern and the contact via.

Inventors

김현우
김동우
김철성
노동현
신태연
최효석

Assignees

삼성전자주식회사

Dates

Publication Date: 20260508
Application Date: 20241030

Claims (10)

Semiconductor pattern extended in the first direction; A plurality of channel structures arranged spaced apart from each other in the first direction on the semiconductor pattern - the plurality of channel structures include a plurality of channel patterns stacked spaced apart from each other in a vertical direction -; A plurality of gate structures surrounding the plurality of channel patterns, each traversing the plurality of channel structures in a second direction intersecting the first direction; Source/drain patterns disposed between the plurality of channel structures on the semiconductor pattern and connected to the sides of the plurality of channel patterns; An insulating separation layer disposed on the lower surface of the above semiconductor pattern; A plurality of insulating separation patterns are respectively disposed in regions corresponding to the plurality of gate structures on the lower surface of the insulating separation layer and each extending toward the plurality of gate structures - the semiconductor pattern is separated into a plurality of pattern regions by the plurality of insulating separation patterns -; A plurality of contact blocks disposed between the plurality of insulating separation patterns on the lower surface of the insulating separation layer; A contact via extending from at least one contact block among the plurality of contact blocks through the insulating separation layer to an adjacent source/drain pattern among the source/drain patterns - the plurality of pattern regions include a first pattern region through which the contact via penetrates and a second pattern region through which the contact via does not penetrate, wherein the first pattern region has an impurity concentration higher than the impurity concentration of the second pattern regions -; and A semiconductor device comprising: a metal-semiconductor compound layer disposed between the first pattern region and the adjacent source/drain pattern and the contact via.
In paragraph 1, It further includes a contact epitaxial layer disposed between the first pattern region and the adjacent source/drain pattern and the metal-semiconductor compound layer, and A semiconductor device in which the contact epitaxial layer comprises a semiconductor element identical to the semiconductor element of the metal-semiconductor compound layer, and the contact epitaxial layer comprises an impurity of the same conductivity type as the impurity of the adjacent source/drain pattern.
In paragraph 2, A semiconductor device in which, in the first pattern region, the impurity concentration in the region in contact with the contact epitaxial layer is greater than the impurity concentration in other regions.
In paragraph 2, A semiconductor device comprising source/drain patterns each having a first epitaxial layer having a first impurity concentration and a second epitaxial layer having a second impurity concentration higher than the first impurity concentration on the first epitaxial layer.
In paragraph 4, The above contact epitaxial layer is a semiconductor device having an impurity concentration higher than the first impurity concentration.
In paragraph 4, A semiconductor device in which, in the first epitaxial layer, the impurity concentration in the region in contact with the contact epitaxial layer is greater than the impurity concentration in other regions.
In paragraph 1, A semiconductor device in which each of the plurality of contact blocks comprises the same metal material as the contact via.
In paragraph 1, A semiconductor device further comprising a conductive barrier disposed between the insulating separation layer and the insulating separation patterns and the plurality of contact blocks, and extending to the surface of the contact via.
Semiconductor pattern extended in the first direction; Device isolation layers disposed on both sides extending in the first direction of the semiconductor pattern; A plurality of channel structures arranged spaced apart from each other in the first direction on the semiconductor pattern; A plurality of gate structures each crossing the plurality of channel structures in a second direction intersecting the first direction; Source/drain patterns disposed between the plurality of channel structures on the semiconductor pattern, comprising a first epitaxial layer having a first impurity concentration and a second epitaxial layer having a second impurity concentration higher than the first impurity concentration on the first epitaxial layer; An insulating separation layer disposed on the lower surface of the above semiconductor pattern; A plurality of insulating separation patterns, each disposed in regions corresponding to the plurality of gate structures on the lower surface of the insulating separation layer, each extending toward the plurality of gate structures and separating the semiconductor pattern into a plurality of pattern regions; A plurality of contact blocks disposed between the plurality of insulating separation patterns on the lower surface of the insulating separation layer; A contact via extending from at least one contact block among the plurality of contact blocks through the insulating separation layer to an adjacent source/drain pattern among the source/drain patterns - the plurality of pattern regions include a first pattern region through which the contact via passes and a second pattern region through which the contact via does not pass -; and A contact epitaxial layer disposed between the first pattern region and the adjacent source/drain pattern and the contact via, having a third impurity concentration higher than the first impurity concentration; A metal-semiconductor compound layer disposed between the contact epitaxial layer and the contact via, comprising a semiconductor element identical to the semiconductor element of the contact epitaxial layer; and A semiconductor device comprising: a wiring structure disposed on the lower surfaces of the plurality of contact blocks and the plurality of insulating separation patterns, and electrically connected to at least one contact block.
In Paragraph 9, The impurities in the above contact epitaxial layer include impurities of the same conductivity type as the impurities in the adjacent source/drain pattern, and A semiconductor device in which the first pattern region has an impurity concentration higher than the impurity concentration of the second pattern regions.

Description

Semiconductor Device The present invention relates to a semiconductor device. As the demand for high performance, high speed, and/or multifunctionality of semiconductor devices increases, the integration density of semiconductor devices is increasing. In line with the trend toward high integration of semiconductor devices, semiconductor devices having a BackSide Power Delivery Network (BSPDN) structure in which power rails are placed on the back side of the wafer are being developed. In addition, efforts are being made to develop semiconductor devices equipped with a channel having a three-dimensional structure in order to overcome the limitations of operating characteristics resulting from the size reduction of planar MOSFETs (metal oxide semiconductor FETs). FIG. 1 is a plan view showing a semiconductor device according to one embodiment of the present invention. Figure 2 is a cross-sectional view of the semiconductor device of Figure 1 taken by cutting along I-I'. FIGS. 3a and 3b are cross-sectional views of the semiconductor device of FIG. 1, cut along II1-II1' and II2-II2', respectively. FIG. 4a is a partial enlarged view showing "A" of the semiconductor device of FIG. 2, and FIG. 4b is a partial enlarged view showing "B" of the semiconductor device of FIG. 3a. FIGS. 5 and FIGS. 6 are side cross-sectional views showing a semiconductor device according to one embodiment of the present invention. FIGS. 7a to 12a and FIGS. 7b to 12b are cross-sectional views of major processes to explain a part of the process (a process for forming an insulation separation pattern) of a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 13a to 16a and FIGS. 13b to 16b are cross-sectional views of major processes to explain a part of the process (backside contact structure formation process) of a method for manufacturing a semiconductor device according to one embodiment of the present invention. Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings. FIG. 1 is a plan view showing a semiconductor device according to one embodiment of the present invention, FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 taken by cutting along I-I', and FIG. 3a and FIG. 3b are cross-sectional views of the semiconductor device of FIG. 1 taken by cutting along II1-II1' and II2-II2', respectively. Referring to FIGS. 1, FIGS. 2, FIGS. 3a, and FIGS. 3b, a semiconductor device (100) according to the present embodiment may include a semiconductor pattern (105P) extended in a first direction (e.g., X direction), a plurality of channel structures (CH) arranged spaced apart in the first direction (e.g., X direction) on the semiconductor pattern (105P), a plurality of gate structures (GS) each crossing the plurality of channel structures (CH) in a second direction (e.g., Y direction) intersecting the first direction (e.g., X direction), and source/drain patterns (150) disposed between the plurality of channel structures (CH). A semiconductor device (100) according to the present embodiment may include a semiconductor pattern (105P) as a base structure for the gate structures (GS) and the source/drain patterns (150). In the present embodiment, the semiconductor pattern (105P) may be part of an "active pattern (105)" that protrudes on the substrate (101) and extends in a first direction (e.g., X direction) before the substrate (101) is ground (see FIG. 8a and FIG. 9a). Referring to FIG. 3a, the device isolation layer (110) may be disposed between semiconductor patterns (105P). The device isolation layer (110) may be disposed on both sides extending in a first direction (e.g., X direction) of the semiconductor patterns (105P). An upper region of the semiconductor pattern (105P) may be exposed from the upper surface of the device isolation layer (110). As illustrated in FIGS. 2 and 3b, channel structures (CH) may be arranged at regular intervals in a first direction (e.g., X direction) on a semiconductor pattern (105P). In this embodiment, channel structures (GS) may include a plurality of channel patterns (130) stacked and spaced apart in a vertical direction (e.g., Z direction) on the semiconductor pattern (105P). The plurality of channel patterns (130) are provided as channel structures (CH) of a transistor and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). In some embodiments, the plurality of channel patterns (130) may be silicon semiconductors. In this embodiment, the plurality of channel patterns (130) are exemplified as three, but their number and shape may be varied. As illustrated in FIGS. 1, 2 and 3b, the gate structure (GS) may include a gate electrode (145) extending in a second direction (e.g., Y direction) and surrounding a plurality of channel patterns (130), a gate insulating film (142) disposed between the gate electrode (145) and the