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KR-20260064947-A - A MASK ASSEMBLY, AND MANUFACTURING METHOD OF THE SAME

KR20260064947AKR 20260064947 AKR20260064947 AKR 20260064947AKR-20260064947-A

Abstract

A mask assembly according to one embodiment of the present invention may include a wafer having defined cell openings, an upper layer having defined upper openings disposed on the upper surface of the wafer and each overlapping with the cell openings, first pattern portions disposed on the upper layer spaced apart from each other in a plane, each having defined pattern openings and each overlapping with the cell openings, a first lower layer disposed on the back surface of the wafer, and a second lower layer disposed below the first lower layer.

Inventors

  • 이종환
  • 박용준

Assignees

  • 삼성디스플레이 주식회사

Dates

Publication Date
20260508
Application Date
20241030

Claims (20)

  1. A wafer with cell openings defined through the upper and lower surfaces; An upper layer disposed on the upper surface of the wafer and having upper openings defined that overlap with each of the cell openings; First pattern portions spaced apart from each other in a plane and disposed on the upper layer, each having defined pattern openings and each overlapping with the cell openings; A first lower layer disposed on the back surface of the wafer; and A mask assembly comprising a second lower layer disposed below the first lower layer.
  2. In Article 1, The upper layer comprises any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon nitric oxide (SiON), and metal nitride, and The above first pattern parts are a mask assembly including another one.
  3. In claim 1, the upper surface of the upper layer is exposed at least partially from the first pattern portions, and The above wafer is a mask assembly containing silicon
  4. In Article 1, A mask assembly in which the distance between adjacent first pattern parts in a plane is 2 mm or more and 5 mm or less.
  5. In Article 1, The above wafer has a planar circular shape, and It further includes dummy pattern parts disposed on the upper layer and spaced apart from the first pattern parts in a plane, A mask assembly in which adjacent dummy pattern portions are symmetrically arranged relative to each other based on an imaginary line passing through the center of the wafer on a plane.
  6. In Article 5, The above dummy pattern portions include the same material as the above first pattern portions and are non-overlapping with the cell openings.
  7. In Article 1, It further includes 2-1 pattern portions disposed on the upper layer and extended in a first direction, and 2-2 pattern portions disposed on the upper layer and extended in a second direction intersecting the first direction. A mask assembly in which the first pattern sections are respectively disposed between the adjacent second-1 pattern sections and the adjacent second-2 pattern sections.
  8. In Article 7, A mask assembly in which the above 2-1 pattern parts and the above 2-2 pattern parts are spaced apart from the above 1 pattern parts by a predetermined distance.
  9. In Article 1, 2-1 pattern sections disposed between adjacent first pattern sections in a first direction and arranged along a second direction intersecting the first direction, and A mask assembly further comprising second-2 pattern parts arranged along the first direction and positioned between the first pattern parts adjacent to each other in the second direction.
  10. In Article 9, A mask assembly further comprising 2-3 pattern parts having an 'X' shape, disposed between adjacent 2-1 pattern parts and adjacent 2-2 pattern parts.
  11. In Article 1, 2-1 pattern sections extending in a first direction and disposed between adjacent first pattern sections in a second direction intersecting the first direction; and A mask assembly further comprising 2-2 pattern parts that extend in the second direction and are spaced apart from each other in the second direction with each of the 2-1 pattern parts in between.
  12. In Article 1, In the first lower layer, first lower openings are defined that overlap with the cell openings on a plane, respectively, and A mask assembly in which second lower openings are defined in the second lower layer, each overlapping with the first lower openings on a plane.
  13. In Article 1, Each of the above cell openings is a mask assembly having a width that decreases in the direction of the back surface of the wafer and the top surface of the wafer.
  14. In Article 1, The above pattern openings overlap with the above cell openings, and A mask assembly in which the ends of the first pattern parts on a plane overlap with the upper layer.
  15. In Article 1, The upper surface of the wafer is in direct contact with the upper layer, and The upper surface of the upper layer is a mask assembly that is in direct contact with the first pattern portion.
  16. Step of providing a wafer; A step of forming an upper layer on the upper surface of the wafer and forming a first lower layer on the back surface of the wafer; A step of forming a pattern layer on the upper surface of the upper layer and forming a second lower layer on the back surface of the first lower layer; A step of etching the above pattern layer to form a pattern portion comprising first pattern portions that are spaced apart from each other on a plane and each have a defined pattern opening; A step of etching the first and second lower layers to form lower openings; and A method for manufacturing a mask assembly comprising the step of etching the wafer from the back surface toward the top surface to form cell openings that overlap with the first pattern portions.
  17. In Article 16, The formation of the upper layer and the formation of the first lower layer are performed simultaneously in a single process, and A method for manufacturing a mask assembly in which the formation of the above pattern layer and the formation of the above second lower layer are performed simultaneously in a single process.
  18. In Article 16, The step of forming the lower openings comprises the step of etching the second lower layer from the back surface toward the top surface to form the second lower opening, and A method for manufacturing a mask assembly comprising the step of etching the first lower layer from the back surface toward the top surface to form a first lower opening.
  19. In Article 16, The method further includes the step of etching the above pattern layer to form a second pattern portion spaced apart from the first pattern portions on a plane. A method for manufacturing a mask assembly in which the step of forming the first pattern portions and the step of forming the second pattern portion are performed simultaneously in a single process.
  20. In Article 16, The step of forming the cell openings is performed by a wet etching process, and A method for manufacturing a mask assembly in which each of the above cell openings has a width that becomes smaller in the direction of the back surface and the top surface of the wafer.

Description

A mask assembly and manufacturing method of the same The present invention relates to a mask assembly and a method for manufacturing the same, and specifically, to a mask assembly with improved reliability of the deposition process and a method for manufacturing the same. A display device includes a plurality of pixels, and each pixel includes a driving element such as a transistor and a display element such as an organic light-emitting diode. The display element can be formed by stacking electrodes and a light-emitting pattern on a substrate. The light emission pattern is patterned using a mask assembly in which holes are defined to be formed in a predetermined area. Meanwhile, since the repetitive use of production equipment is required for the mass production of display panels, research is necessary to provide production equipment with improved reliability. FIG. 1 is a perspective view of an electronic device according to one embodiment of the present invention. FIG. 2 is a diagram showing the use of an electronic device according to one embodiment of the present invention. FIG. 3 is an exploded perspective view showing a part of an electronic device according to one embodiment of the present invention. FIG. 4 is a cross-sectional view of a deposition apparatus according to one embodiment of the present invention. FIG. 5a is a plan view of a mask assembly according to one embodiment of the present invention. Figure 5b is an enlarged plan view of the AA' region of Figure 5a. FIG. 6 is a cross-sectional view of a mask assembly according to a comparative example. FIG. 7 is a cross-sectional view of a mask assembly along line I-I' of FIG. 6. FIG. 8 is a block diagram of a method for manufacturing a mask assembly according to one embodiment of the present invention. FIGS. 9a to 9h each illustrate a step of a method for manufacturing a mask assembly according to one embodiment of the present invention. FIG. 10 is a plan view of a mask assembly according to one embodiment of the present invention. Figure 11 is an enlarged plan view of the BB' area of Figure 10. FIG. 12 is a cross-sectional view of a mask assembly along line II-II' of FIG. 11. FIG. 13 is a block diagram of a method for manufacturing a mask assembly according to one embodiment of the present invention. FIGS. 14a and FIGS. 14b are drawings illustrating each step of a method for manufacturing a mask assembly according to one embodiment of the present invention. FIG. 15 is an enlarged plan view of a part of a mask assembly according to one embodiment of the present invention. FIG. 16 is an enlarged plan view of a part of a mask assembly according to one embodiment of the present invention. FIG. 17 is an enlarged plan view of a part of a mask assembly according to one embodiment of the present invention. FIG. 18 is a plan view of a mask assembly according to one embodiment of the present invention. FIG. 19 is a plan view of a display panel manufactured using the mask assembly shown in FIG. 4. FIG. 20 is a cross-sectional view of a single pixel shown in FIG. 19. FIG. 21 is a diagram for explaining a deposition process by the deposition apparatus shown in FIG. 4. The present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed/connected/joined on the other component, or that a third component may be placed between them. Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And/or” includes all one or more combinations that the associated components may define. Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise. Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings. Terms such as "include