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KR-20260065036-A - GATE DRIVER AND ELECTRONIC DEVICE INCLUDING THE SAME

KR20260065036AKR 20260065036 AKR20260065036 AKR 20260065036AKR-20260065036-A

Abstract

The gate driver includes a plurality of stages. Each of the stages includes a CQ node charging circuit, a first CQS node charging circuit, a second CQS node charging circuit, a QB node control circuit, a CQ node boosting circuit, and a gate output circuit that outputs first to P gate clock signals (where P is a positive integer greater than or equal to 2) as first to P gate signals. The stages receive first to Q gate clock signals (where Q is a positive integer greater than P). Q may be the minimum value among Q values that satisfy the condition that the interval in which the Q+1 gate signal of the second stage is output is separated from the interval in which the voltage of the CQ node of the first stage has a high level.

Inventors

  • 김경호
  • 유병창
  • 하진주

Assignees

  • 삼성디스플레이 주식회사

Dates

Publication Date
20260508
Application Date
20241031

Claims (20)

  1. In a gate driving unit comprising a plurality of stages, Each of the above stages is, A CQ node charging circuit that provides the previous carry signal and a second high gate voltage to the CQ node in response to the previous carry signal; A first CQS node charging circuit that provides the second high gate voltage to the CQS node in response to the previous carry signal; A second CQS node charging circuit that provides a first high gate voltage to the CQS node in response to the voltage of the boosting node; QB node control circuit that inverts the voltage of the above CQ node and provides it to the QB node; A CQ node boosting circuit that provides a boosting clock signal to the boosting node in response to the voltage of the CQ node and provides a second low gate voltage to the boosting node in response to the voltage of the QB node; and It includes a gate output circuit that outputs first to P gate clock signals (where P is a positive integer greater than or equal to 2) as first to P gate signals in response to the voltage of the CQ node, and outputs a first low gate voltage as the first to P gate signals in response to the voltage of the QB node. Each pulse of the first to P gate signals is included in the interval where the voltage of the boosting node has a high level, and the interval where the voltage of the boosting node has a high level is included in the interval where the voltage of the CQ node has a high level. The above stages receive first to Q gate clock signals (where Q is a positive integer greater than P), and A gate driving unit characterized in that, when a first stage outputs first to P gate clock signals as first to P gate signals and a second stage receives P+1 to Q gate clock signals and outputs them as P+1 to Q gate signals, and the second stage receives a first gate clock signal and outputs it as a Q+1 gate signal, the section where the Q+1 gate signal is output is spaced apart from the section where the voltage of the CQ node of the first stage has the high level.
  2. A gate driving unit according to claim 1, characterized in that Q is a multiple of 2.
  3. A gate driver according to claim 1, wherein Q is a minimum value satisfying the condition that the section in which the second stage outputs the Q+1 gate signal is separated from the section in which the voltage of the CQ node of the first stage has the high level.
  4. A gate driver according to claim 1, wherein the gate driver supports a Dual Line Gate (DLG) mode, and while the gate driver performs the DLG mode, the time length of the pulse of each of the first to Q gate clock signals is reduced.
  5. A gate driver according to claim 1, characterized in that P is 6 and Q is 10.
  6. In claim 1, the CQ node charging circuit is, A first-1 transistor comprising a gate electrode receiving the previous carry signal, a first electrode receiving the previous carry signal, and a second electrode receiving the second high gate voltage; and A gate driver comprising a first-2 transistor including a gate electrode receiving the previous carry signal, a first electrode receiving the second high gate voltage, and a second electrode connected to the CQ node.
  7. In Article 1, The above-mentioned first CQS node charging circuit is, A fourth transistor comprising a gate electrode receiving the previous carry signal, a first electrode receiving the second high gate voltage, and a second electrode connected to the CQS node, and The above second CQS node charging circuit is, A gate driver comprising a fifth transistor including a gate electrode receiving the voltage of the boosting node, a first electrode receiving the first high gate voltage, and a second electrode connected to the CQS node.
  8. In claim 1, the QB node control circuit is, A seventh transistor comprising a gate electrode receiving the first high gate voltage, a first electrode receiving the first high gate voltage, and a second electrode; An eighth transistor comprising a gate electrode connected to the second electrode of the seventh transistor, a first electrode receiving the first high gate voltage, and a second electrode connected to the QB node; A ninth transistor comprising a gate electrode connected to the CQ node, a first electrode receiving the first low gate voltage, and a second electrode connected to the second electrode of the seventh transistor and the gate electrode of the eighth transistor; and A gate driver comprising a 10th transistor including a gate electrode connected to the CQ node, a first electrode receiving the second low gate voltage, and a second electrode connected to the QB node.
  9. In claim 1, the CQ node boosting circuit is, A first transistor comprising a gate electrode connected to the CQ node, a first electrode receiving the boosting clock signal, and a second electrode connected to the boosting node; A 12th transistor comprising a gate electrode connected to the QB node, a first electrode receiving the second low gate voltage, and a second electrode connected to the boosting node; and A gate driver comprising a CQ boost capacitor including a first electrode connected to the CQ node and a second electrode connected to the boosting node.
  10. In claim 1, the gate output circuit comprises first to P gate output circuits that output the first to P gate signals, and The above P-gate output circuit is, A P-gate variable-on transistor comprising a gate electrode connected to the CQS node, a first electrode connected to the CQ node, and a second electrode connected to the P-gate Q node; A 15-P transistor comprising a gate electrode connected to the P gate Q node, a first electrode receiving the P gate clock signal, and a second electrode connected to the P gate node where the P gate signal is output; A 16-P transistor comprising a gate electrode connected to the QB node, a first electrode receiving the first low gate voltage, and a second electrode connected to the P gate node; and A gate driver comprising a P gate boost capacitor including a first electrode connected to the P gate Q node and a second electrode connected to the boosting node.
  11. In claim 1, each of the above stages is, A first CQ node discharge circuit that provides the second low gate voltage to the CQ node in response to the next carry signal; and A gate driver further comprising a second CQ node discharge circuit that provides the second low gate voltage to the CQ node in response to the voltage of the above QB node.
  12. In Article 11, The above first CQ node discharge circuit is, It includes a second transistor comprising a gate electrode receiving the next carry signal, a first electrode receiving the second low gate voltage, and a second electrode connected to the CQ node, and The above second CQ node discharge circuit is, A gate driver comprising a gate electrode connected to the QB node, a first electrode receiving the second low gate voltage, and a third transistor including a second electrode connected to the CQ node.
  13. In claim 1, each of the above stages is, A gate driver further comprising a third CQS node charging circuit that provides the first high gate voltage to the CQS node in response to the next carry signal.
  14. In Article 13, The above third CQS node charging circuit is, A gate driver comprising a sixth transistor including a gate electrode receiving the next carry signal, a first electrode receiving the first high gate voltage, and a second electrode connected to the CQS node.
  15. In claim 1, each of the above stages is, A gate driver further comprising a CQS node discharge circuit that provides the first low gate voltage to the CQS node in response to the voltage of the above QB node.
  16. In Article 15, The above CQS node discharge circuit is, A gate driver comprising a 19th transistor including a gate electrode connected to the QB node, a first electrode receiving the first low gate voltage, and a second electrode connected to the CQS node.
  17. In claim 1, each of the above stages is, A gate driver further comprising a carry output circuit that outputs a carry clock signal as a carry signal in response to the voltage of the CQ node and outputs a second low gate voltage as a carry signal in response to the voltage of the QB node.
  18. In claim 17, the carry output circuit is, A carry variable-on transistor comprising a gate electrode connected to the CQS node, a first electrode connected to the CQ node, and a second electrode connected to the carry Q node; A 13th transistor comprising a gate electrode connected to the carry Q node, a first electrode receiving the carry clock signal, and a second electrode connected to the carry node where the carry signal is output; A 14th transistor comprising a gate electrode connected to the QB node, a first electrode receiving the second low gate voltage, and a second electrode connected to the carry node; and A gate driver comprising a carry boost capacitor including a first electrode connected to the carry Q node and a second electrode connected to the carry node.
  19. A display panel containing pixels; A data driving unit that provides data voltage to the above pixel; A gate driver that provides a gate signal to the above pixel; A driving control unit that controls the data driving unit and the gate driving unit; and It includes a power supply that supplies power to the display panel, the data driving unit, the gate driving unit, and the driving control unit. The above gate driving unit includes a plurality of stages, and Each of the above stages is, A CQ node charging circuit that provides the previous carry signal and a second high gate voltage to the CQ node in response to the previous carry signal; A first CQS node charging circuit that provides the second high gate voltage to the CQS node in response to the previous carry signal; A second CQS node charging circuit that provides a first high gate voltage to the CQS node in response to the voltage of the boosting node; QB node control circuit that inverts the voltage of the above CQ node and provides it to the QB node; A CQ node boosting circuit that provides a boosting clock signal to the boosting node in response to the voltage of the CQ node and provides a second low gate voltage to the boosting node in response to the voltage of the QB node; and It includes a gate output circuit that outputs first to P gate clock signals (where P is a positive integer greater than or equal to 2) as first to P gate signals in response to the voltage of the CQ node, and outputs a first low gate voltage as the first to P gate signals in response to the voltage of the QB node. Each pulse of the first to P gate signals is included in the interval where the voltage of the boosting node has a high level, and the interval where the voltage of the boosting node has a high level is included in the interval where the voltage of the CQ node has a high level. The above stages receive first to Q gate clock signals (where Q is a positive integer greater than P), and An electronic device characterized in that, when a first stage outputs first to P gate clock signals as first to P gate signals and a second stage receives P+1 to Q gate clock signals and outputs them as P+1 to Q gate signals, and the second stage receives a first gate clock signal and outputs it as a Q+1 gate signal, the section where the Q+1 gate signal is output is spaced apart from the section where the voltage of the CQ node of the first stage has the high level.
  20. An electronic device according to claim 19, characterized in that Q is a multiple of 2.

Description

Gate driver and electronic device including the same The present invention relates to a gate driver and an electronic device including the same, and more specifically, to a gate driver that supports a Dual Line Gate (DLG) mode and an electronic device including the same. Recently, a display device supporting DLG (Dual Line Gate) mode has been developed. The DLG mode refers to a mode that increases the driving frequency of the display device by using a method of simultaneously driving two consecutive gate lines. For example, when the display device supports up to 60 Hz, the display device can support up to 120 Hz by using the DLG mode. Meanwhile, the display device supporting the DLG mode may include a gate driver that outputs a gate signal to the gate line, and the configuration of the gate driver may be numerous. In particular, the number of gate clock signals of the gate driver may be large. When the number of gate clock signals of the gate driver is large, the dead space of the gate driver may increase. FIG. 1 is a block diagram showing a display device according to embodiments of the present invention. Figure 2 is a block diagram showing an example of a pixel of Figure 1. Figure 3 is a block diagram showing the gate driving unit of Figure 1. Figure 4 is a circuit diagram showing the stage of Figure 3. Figure 5 is a timing diagram showing the operation of the stage of Figure 4. Figure 6 is a circuit diagram showing the operation of the stage of Figure 4 in the first section of Figure 5. Figure 7 is a circuit diagram showing the operation of the stage of Figure 4 in the second section of Figure 5. FIG. 8 is a circuit diagram showing the operation of the stage of FIG. 4 in the third section of FIG. 5. FIG. 9 is a circuit diagram showing the operation of the stage of FIG. 4 in the fourth section of FIG. 5. Figures 10 and 11 are conceptual diagrams illustrating the number of clock signals. FIG. 12 is a block diagram showing an electronic device according to embodiments of the present invention. FIG. 13 is a diagram showing an example in which the electronic device of FIG. 10 is implemented as a smartphone. Hereinafter, the present invention will be described in more detail with reference to the attached drawings. Hereinafter, the present invention will be described in more detail with reference to the attached drawings. FIG. 1 is a block diagram showing a display device (100) according to embodiments of the present invention. Referring to FIG. 1, the display device (100) includes a display panel (110) and a display panel driver. The display panel driver may include a drive control unit (120), a gate driver (130), a gamma reference voltage generator (140), and a data driver (150). The above display panel (110) may include a display portion for displaying an image and a peripheral portion disposed adjacent to the display portion. The display panel (110) may include gate lines (GL), data lines (DL), and pixels (PX) electrically connected to each of the gate lines (GL) and the data lines (DL). The gate lines (GL) may extend in a first direction, and the data lines (DL) may extend in a second direction that intersects the first direction. The above-described drive control unit (120) can receive input image data (IMG) and input control signals (CONT) from an external device (not shown). For example, the input image data (IMG) may include red image data, green image data, and blue image data. The input image data (IMG) may include white image data. The input image data (IMG) may include magenta image data, yellow image data, and cyan image data. The input control signals (CONT) may include a master clock signal and a data enable signal. The input control signals (CONT) may further include a vertical synchronization signal and a horizontal synchronization signal. The above driving control unit (120) can generate a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3), and a data signal (DATA) based on the input image data (IMG) and the input control signal (CONT). The above drive control unit (120) can generate the first control signal (CONT1) for controlling the operation of the gate drive unit (130) based on the input control signal (CONT) and provide it to the gate drive unit (130). The first control signal (CONT1) may include a vertical start signal and a gate clock signal. The above drive control unit (120) may generate the second control signal (CONT2) for controlling the operation of the data drive unit (150) based on the input control signal (CONT) and provide it to the data drive unit (150). The second control signal (CONT2) may include a horizontal start signal and a load signal. The above drive control unit (120) can generate a data signal (DATA) based on the input image data (IMG). The above drive control unit (120) can provide the data signal (DATA) to the data drive unit (150). The above driving control unit (120) can generate the third control signal (CONT3) to