KR-20260065067-A - DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING THE SAME

Abstract

A display panel comprises a plurality of pixels arranged along a first direction, a first type stage including a plurality of first buffer circuits each outputting a plurality of first type scan signals to the plurality of pixels, a second type stage including a plurality of second buffer circuits each outputting a plurality of second type scan signals to the plurality of pixels, and a plurality of carry clock lines disposed between the plurality of first buffer circuits and the second buffer circuits and extending along the first direction, wherein the plurality of first buffer circuits are arranged along the first direction and the plurality of second buffer circuits may be arranged along the first direction.

Inventors

• 박도영
• 김경호
• 김윤미
• 김형석
• 신동희
• 유병창
• 하진주

Assignees

• 삼성디스플레이 주식회사

Dates

Publication Date

20260508

Application Date

20241031

Claims (20)

1. Multiple pixels arranged along a first direction; A first type stage comprising a plurality of first buffer circuits that each output a plurality of first type scan signals to the plurality of pixels; A second type stage comprising a plurality of second buffer circuits that each output a plurality of second type scan signals to the plurality of pixels; and It includes a plurality of carry clock wires disposed between the plurality of first buffer circuits and the second buffer circuits and extending along the first direction, The plurality of first buffer circuits are arranged along the first direction, and The plurality of second buffer circuits are a display panel arranged along the first direction.
2. In Article 1, A plurality of first-type clock wires electrically connected to the first-type stage; and It further includes a plurality of second-type clock wires electrically connected to the second-type stage, and The first type clock wiring and the second type clock wiring are spaced apart in a second direction intersecting the first direction, and the plurality of carry clock wirings are arranged between the first type clock wiring and the second type clock wiring in a display panel.
3. In Article 2, The first type stage is positioned between the first type clock wirings and the plurality of carry clock wirings, and The second type stage is a display panel disposed between the second type clock wirings and the plurality of carry clock wirings.
4. In Article 2, The above-mentioned first type stage further includes a first logic circuit that controls the operation of the plurality of first buffer circuits, and The above-mentioned second type stage further includes a second logic circuit that controls the operation of the plurality of second buffer circuits, and The plurality of first buffer circuits are positioned between the first type clock wirings and the first logic circuit, and The plurality of second buffer circuits above are a display panel disposed between the second type clock wiring and the second logic circuit.
5. In Article 2, A display panel in which the plurality of first-type clock lines, the first-type stage, the carry clock lines, the second-type stage, the plurality of second-type clock lines, and the plurality of pixels are sequentially arranged in the second direction.
6. In Article 5, A display panel further comprising a voltage wiring disposed between the plurality of second-type clock wirings and the plurality of pixels, wherein the voltage wiring extends along the first direction.
7. In Article 5, A display panel further comprising a voltage wiring disposed between the first type stage and the second type stage, wherein the voltage wiring extends along the first direction.
8. In Article 1, It further includes a plurality of signal wires electrically connected to the first type stage and the second type stage, and The plurality of signal wires are a display panel disposed between the plurality of first buffer circuits and the plurality of second buffer circuits.
9. In Article 8, A first connecting wire extending along a second direction intersecting the first direction; and It further includes a second connecting wire that is spaced apart from the first connecting wire and along the second direction and extends along the second direction, The first connecting wire is electrically connected to one of the plurality of signal wires and the first type stage, and the second connecting wire is electrically connected to the one signal wire and the second type stage, forming a display panel.
10. In Article 8, A display panel further comprising an integrated logic circuit disposed between the plurality of signal lines and the plurality of clock lines and controlling the operation of the plurality of first buffer circuits and the plurality of second buffer circuits.
11. In Article 1, A plurality of first type scan wires electrically connected in a one-to-one correspondence with the plurality of first buffer circuits; and It further includes a plurality of second type scan wires electrically connected in a one-to-one correspondence with the plurality of second buffer circuits above, and A display panel in which the plurality of first-type scan lines and the plurality of second-type scan lines are electrically connected to the plurality of pixels across an inlet area adjacent to the plurality of pixels.
12. In Article 11, A display panel in which at least some of the plurality of second type scan lines are disposed between some of the plurality of first type scan lines and other first type scan lines in the above-mentioned inlet area.
13. In Article 11, Data wiring electrically connected to the plurality of pixels above; and It further includes power wiring electrically connected to the plurality of pixels mentioned above, and Each of the above plurality of pixels includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit, and The pixel driving circuit comprises a first transistor connected between the power wiring and the light-emitting element, a second transistor connected between the data wiring and the gate electrode of the first transistor, and a third transistor connected between the light-emitting element and the read-out wiring, forming a display panel.
14. In Article 13, The operation of the second transistor is controlled by one of the plurality of first type scan signals, and The above third transistor is a display panel whose operation is controlled by one of the plurality of second-type scan signals.
15. In Article 13, The operation of the second transistor is controlled by one of the plurality of second type scan signals, and The above third transistor is a display panel whose operation is controlled by one of the plurality of first type scan signals.
16. A display panel defined with a display area and a non-display area adjacent to the display area; and It includes a data driving circuit electrically connected to the above-mentioned display panel, and The above display panel is, A plurality of pixels arranged along a first direction in the above-mentioned display area; The above display panel comprises a plurality of pixels and data wiring electrically connected to the data driving circuit; A first type stage disposed in the above non-display area and outputting a plurality of first type scan signals to the plurality of pixels; and It includes a second type stage disposed in the above non-display area and outputting a plurality of second type scan signals to the plurality of pixels, and The first type stage and the second type stage are electronic devices spaced apart in a second direction intersecting the first direction.
17. In Article 16, The above-mentioned first type stage includes a plurality of first buffer circuits that each output the plurality of first type scan signals, and The above-mentioned second type stage includes a plurality of second buffer circuits that output the plurality of second type scan signals, respectively, and The plurality of first buffer circuits are arranged along the first direction, and The plurality of second buffer circuits above are electronic devices arranged along the first direction.
18. In Article 17, The above display panel is, A plurality of carry clock wires disposed between the plurality of first buffer circuits and the second buffer circuits and extending along the first direction; A plurality of first-type clock wires electrically connected to the first-type stage; and It further includes a plurality of second-type clock wires electrically connected to the second-type stage, and An electronic device in which the first type clock wiring and the second type clock wiring are spaced apart in the second direction, and the plurality of carry clock wirings are positioned between the first type clock wiring and the second type clock wiring.
19. In Article 18, The plurality of first type clock wires, the first type stage, the carry clock wires, the second type stage, the plurality of second type clock wires, and the plurality of pixels are sequentially arranged in the second direction, and The above display panel further includes voltage wiring disposed between the plurality of second-type clock wirings and the plurality of pixels, and the voltage wiring extends along the first direction.
20. In Article 17, The above display panel further includes a plurality of signal wires electrically connected to the first type stage and the second type stage, a first connecting wire extending along the second direction, and a second connecting wire spaced apart from the first connecting wire along the second direction and extending along the second direction. The plurality of signal wires are arranged between the plurality of first buffer circuits and the plurality of second buffer circuits, and An electronic device in which the first connecting wire is electrically connected to one of the plurality of signal wires and the first type stage, and the second connecting wire is electrically connected to the one signal wire and the second type stage.

Description

Display panel and electronic device including the same The present invention relates to a display panel with a reduced width of the non-display area and an electronic device including the same. Multimedia electronic devices such as televisions, mobile phones, tablets, computers, navigation systems, and game consoles include display panels for displaying images. In response to market demands, research is underway to reduce the non-display area (non-display area or bezel area) on the display panel. FIG. 1a is a perspective view of an electronic device according to one embodiment of the present invention. FIG. 1b is a block diagram of an electronic device according to one embodiment of the present invention. FIG. 2 is a plan view of an electronic device according to one embodiment of the present invention. FIG. 3 is a block diagram of an electronic device according to one embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of a pixel according to one embodiment of the present invention. FIG. 5 is a block diagram illustrating some components of an electronic device according to one embodiment of the present invention. FIG. 6a is a drawing illustrating a scan driving circuit according to one embodiment of the present invention. FIG. 6b is an equivalent circuit diagram illustrating one stage according to one embodiment of the present invention. FIG. 7 is a timing diagram for explaining the operation of a stage in a first mode according to an embodiment of the present invention. FIG. 8 is a timing diagram of a plurality of clock signals for explaining the operation of a stage in a second mode according to an embodiment of the present invention. FIG. 9 is a diagram illustrating the activation state and changes in brightness of a first type scan signal and a second type scan signal according to an embodiment of the present invention. FIG. 10 is a diagram illustrating the activation state and changes in brightness of a first type scan signal and a second type scan signal according to an embodiment of the present invention. FIG. 11 is a plan view of a part of a display panel according to one embodiment of the present invention. FIG. 12a is a plan view illustrating one signal wiring and a plurality of cross signal wirings according to a comparative example of the present invention. FIG. 12b is a plan view illustrating one signal wiring and a plurality of cross signal wirings according to one embodiment of the present invention. FIG. 12c is a plan view illustrating one signal wiring according to one embodiment of the present invention. FIG. 13 is a plan view illustrating some of the signal wiring according to one embodiment of the present invention. FIG. 14 is a plan view of a part of a display panel according to one embodiment of the present invention. FIG. 15 is a plan view of a part of a display panel according to one embodiment of the present invention. FIG. 16 is a plan view of a part of a display panel according to one embodiment of the present invention. FIG. 17 is a plan view of a part of a display panel according to one embodiment of the present invention. In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed/connected/joined on the other component, or that a third component may be placed between them. Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And/or” includes all one or more combinations that the associated components may define. Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise. Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings. Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. The terms "part" and "unit" refer to software components or hardware components that perform specific functions. Hardware components m