KR-20260065195-A - Semiconductor device and method of failure analysis for the same

Abstract

The present invention provides a semiconductor device and a method for analyzing defects therein. The semiconductor device comprises: a substrate having a front surface and a back surface opposite to each other; a first transistor disposed on the front surface of the substrate and comprising a first gate electrode and first source/drain patterns adjacent to both sides thereof; and a front dummy stack structure located on the first transistor and electrically floating, wherein the front dummy stack structure comprises front dummy vias and front dummy wirings that are alternately stacked, and the front dummy vias and front dummy wirings constituting the front dummy stack structure are vertically superimposed with the first gate electrode.

Inventors

• 정명진
• 김진규
• 정은국
• 조근휘
• 허수행

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20241101

Claims (10)

1. A substrate including a front and a back surface opposite each other; A first transistor disposed on the front surface of the substrate and comprising a first gate electrode and first source/drain patterns adjacent to both sides thereof; and A front dummy stack structure located on the first transistor and electrically floating, comprising: The above-described front dummy stack structure includes front dummy vias and front dummy wirings that are alternately stacked, and The front dummy vias and front dummy wiring constituting the front dummy stack structure are a semiconductor device that overlaps vertically with the first gate electrode.
2. In Article 1, A first wiring structure connected to the first gate electrode and one of the first source/drain patterns; and The structure further includes an upper insulating film covering the first wiring structure and the front dummy stack structure, wherein The first wiring structure above includes front vias and front wirings that are alternately stacked, and The upper level of the first wiring structure is a semiconductor device that is the same as the upper level of the front dummy stack structure.
3. In Article 2, The uppermost of the above front wirings is a semiconductor device that does not overlap vertically with the above front dummy vias and the above front dummy wirings.
4. In Article 2, A semiconductor device further comprising a supporting substrate on the upper insulating film.
5. In Article 1, The first transistor above is a semiconductor device included in a first flip-flop circuit.
6. In Article 5, A semiconductor device in which a test signal is input to the first gate electrode of the first transistor.
7. In Article 1, It further includes power wiring disposed on the rear surface of the above substrate, The above power wiring is a semiconductor device connected to one of the first source/drain patterns of the first transistor.
8. In Article 1, A second transistor disposed on the front surface of the substrate and comprising a second gate electrode and second source/drain patterns adjacent to both sides thereof; A first power wiring disposed on the rear surface of the substrate and connected to one of the second source/drain patterns; and The structure further comprises a rear dummy stack structure disposed on the rear surface of the substrate and electrically floating, wherein The above-described rear dummy stack structure includes rear dummy vias and rear dummy wirings that are alternately stacked, and The back dummy vias and back dummy wiring constituting the back dummy stack structure are a semiconductor device that overlaps vertically with the second gate electrode.
9. A substrate including a front and a back surface opposite each other; A first transistor disposed on the front surface of the substrate and comprising a first gate electrode and first source/drain patterns adjacent to both sides thereof; A first power wiring disposed on the rear surface of the substrate and connected to one of the first source/drain patterns; and A rear dummy stack structure disposed on the rear surface of the substrate and electrically floating, comprising: The above-described rear dummy stack structure includes rear dummy vias and rear dummy wirings that are alternately stacked, and The back dummy vias and back dummy wiring constituting the back dummy stack structure are a semiconductor device that overlaps vertically with the first gate electrode.
10. A substrate including a front and a back surface opposite each other; A first flip-flop circuit and a second flip-flop circuit disposed on the front surface of the above substrate; A first transistor disposed on the front surface of the substrate and comprising a first gate electrode and first source/drain patterns adjacent to both sides thereof, wherein the first transistor is included in the first flip-flop circuit; A second transistor disposed on the front surface of the substrate and comprising a second gate electrode and second source/drain patterns adjacent to both sides thereof, wherein the second transistor is included in the second flip-flop circuit; A front dummy stack structure located on the first transistor and electrically floating; A first wiring structure disposed on the front surface of the substrate and connected to the first gate electrode and one of the first source/drain patterns; A first power wiring disposed on the rear surface of the substrate and connected to one of the second source/drain patterns; A rear dummy stack structure disposed on the rear surface of the above substrate and electrically floating; and It includes a second wiring structure disposed on the rear surface of the above substrate and connected to the first power wiring, The above-described front dummy stack structure includes front dummy vias and front dummy wirings that are alternately stacked, and The front dummy vias and front dummy wiring constituting the front dummy stack structure are vertically superimposed with the first gate electrode, and The above-described rear dummy stack structure includes rear dummy vias and rear dummy wirings that are alternately stacked, and The back dummy vias and back dummy wiring constituting the back dummy stack structure are a semiconductor device that overlaps vertically with the second gate electrode.

Description

Semiconductor device and method of failure analysis for the same The present invention relates to a semiconductor device and a method for analyzing defects therein. Semiconductor devices include integrated circuits composed of Metal Oxide Semiconductor (MOS) FETs. As the size and design rules of semiconductor devices gradually shrink, the scale-down of MOS FETs is also accelerating. This reduction in the size of MOS FETs can lead to defects or failures in semiconductor devices. Failure analysis is widely used in the semiconductor industry and can detect defects in semiconductor devices such as integrated circuits. However, as the design of semiconductor devices becomes more complex, the accuracy of defect detection is declining. FIG. 1 is a cross-sectional view of a semiconductor device according to embodiments of the present invention. FIGS. 2a to 2c are enlarged drawings of 'P1' of FIG. 1 according to embodiments of the present invention. FIG. 3 is a cross-sectional view of a first transistor according to embodiments of the present invention. FIGS. 4a and 4b are enlarged drawings of 'P2' of FIG. 1 according to embodiments of the present invention. FIGS. 5A and FIGS. 5B are plan views of a portion of a semiconductor device according to embodiments of the present invention. FIGS. 6a to 6d are plan views of a portion of a semiconductor device according to embodiments of the present invention. FIGS. 7a and 7b are conceptual diagrams of semiconductor devices according to embodiments of the present invention. FIGS. 8a and FIGS. 8b are conceptual diagrams of semiconductor devices according to embodiments of the present invention. FIG. 9 is a flowchart illustrating a method for analyzing defects in a semiconductor device according to embodiments of the present invention. FIG. 10 is a schematic diagram illustrating a method for analyzing defects in a semiconductor device according to embodiments of the present invention. Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. In this specification, terms indicating order, such as first, second, etc., are used to distinguish components having the same or similar functions from one another, and the numbers may change depending on the order in which they are mentioned. FIG. 1 is a cross-sectional view of a semiconductor device according to embodiments of the present invention. FIG. 2a to 2c are enlarged views of ‘P1’ of FIG. 1 according to embodiments of the present invention. FIG. 3 is a cross-sectional view of a first transistor according to embodiments of the present invention. FIG. 3 shows a cross-section cut along the longitudinal direction (D1) of the first gate electrode (GE1) of the first transistor (TR1) of FIG. 1. FIG. 4a and 4b are enlarged views of ‘P2’ of FIG. 1 according to embodiments of the present invention. Referring to FIGS. 1, FIGS. 2a and FIGS. 4a, a semiconductor device (1000) according to the present example includes a substrate (100). The substrate (100) may be a semiconductor substrate including silicon, germanium, silicon-germanium, etc., a compound semiconductor substrate, or an insulating substrate made of an insulating material such as silicon oxide. The substrate (100) may include a front surface (100F) and a rear surface (100B) that are opposite to each other. Transistors (TR1, TR2) are disposed on the front surface (100F) of the substrate (100). The first transistor (TR1) may include a first gate electrode (GE1) and first and second source/drain patterns (SD11, SD12) adjacent to both sides thereof. The second transistor (TR2) may include a second gate electrode (GE2) and second and second source/drain patterns (SD21, SD22) adjacent to both sides thereof. The above transistors (TR1, TR2) have the form of a Multi-Bridge Channel FET (MBCFET), but the present invention is not limited thereto, and the above transistors (TR1, TR2) may have the form of a planar FET, FinFET, Vertical FET, BCAT (Buried Channel Array Transistor), or GAAFET (Gate all around FET). An active pattern (AP) can be defined by a trench (TC) formed on the upper surface of the substrate (100). The active pattern (AP) may be a vertically protruding portion as part of the substrate (100). Multiple active patterns (AP) may be provided. Some of the active patterns (AP) may be provided in a PMOSFET region, and other parts of the active patterns (AP) may be provided in an NMOSFET region. The device isolation layer (ST) can fill the trench (TC). The device isolation layer (ST) may include a silicon oxide film. The device isolation layer (ST) may not cover the first and second channel patterns (CH1, CH2) to be described later. Referring to FIG. 3, a first channel pattern (CH1) may be provided on one of the active patterns (AP). A second channel pattern (CH2) may be provided on the other of the active patterns (AP). Each of the first channe