KR-20260065261-A - SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package may include a first double-chip structure comprising a first semiconductor chip, a second semiconductor chip, and a first scribe lane region, and having a plurality of first through holes in the first scribe lane region; a second double-chip structure stacked on the first double-chip structure, comprising a third semiconductor chip, a fourth semiconductor chip, and a second scribe lane region, and having a plurality of second through holes in the second scribe lane region; first conductive connecting members interposed between the first double-chip structure and the second double-chip structure; and a molding member covering the first and second double-chip structures and filling the first through holes and the second through holes.

Inventors

• 박혜선
• 이용관

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20241101

Claims (10)

1. A first double-chip structure comprising a first semiconductor chip, a second semiconductor chip, and a first scribe lane region separating the first semiconductor chip and the second semiconductor chip, and having a plurality of first through holes formed in the first scribe lane region; A second double-chip structure having a plurality of second through holes formed in the second scribe lane region, comprising a third semiconductor chip disposed on the first semiconductor chip, a fourth semiconductor chip disposed on the second semiconductor chip, and a second scribe lane region separating the third semiconductor chip and the fourth semiconductor chip, wherein the second double-chip structure is stacked on the first double-chip structure and has a plurality of second through holes formed in the second scribe lane region; A plurality of first conductive connecting members interposed between the first double-chip structure and the second double-chip structure, electrically connecting the first semiconductor chip and the third semiconductor chip and electrically connecting the second semiconductor chip and the fourth semiconductor chip; and A semiconductor package comprising a molding member that covers the first and second double-chip structures and fills the plurality of first through holes and the plurality of second through holes.
2. In claim 1, the plurality of first through holes and the plurality of second through holes each overlap each other when viewed in a plan view.
3. A semiconductor package according to claim 1, wherein, when viewed in a plan view, the plurality of first through holes and the plurality of second through holes are arranged alternately with each other.
4. In claim 1, each of the plurality of first through holes has a first diameter, and each of the plurality of second through holes has a second diameter equal to the first diameter, in a semiconductor package
5. A semiconductor package according to claim 1, wherein each of the at least one first through-hole has a first diameter, and each of the at least one second through-hole has a second diameter different from the first diameter.
6. In Article 1, A semiconductor package further comprising a substrate structure having a mounting area in which a first double-chip structure and a second double-chip structure are sequentially mounted.
7. A semiconductor package according to claim 6, wherein the first diameter of each of the plurality of first through holes becomes narrower as it approaches the substrate structure, and the second diameter of each of the plurality of second through holes becomes narrower as it approaches the substrate structure.
8. In claim 6, the first double-chip structure comprises a plurality of first through-vias provided within the first semiconductor chip to electrically connect the substrate structure and the third semiconductor chip, and a plurality of second through-vias provided within the second semiconductor chip to electrically connect the substrate structure and the fourth semiconductor chip, forming a semiconductor package.
9. In Article 6, A semiconductor package further comprising a plurality of second conductive connecting members interposed between the substrate structure and the first double-chip structure and electrically connecting the substrate structure and the first double-chip structure.
10. A substrate structure having a mounting area; A first double-chip structure stacked on the mounting area of the substrate structure, comprising a first scribe lane area separating a pair of first semiconductor chips arranged in a first horizontal direction relative to each other, and a first penetration portion penetrating the first scribe lane area; A second double-chip structure stacked on the first double-chip structure, comprising a pair of second semiconductor chips arranged in the first horizontal direction relative to each other and a second scribe lane region separating the pair of second semiconductor chips, and a second penetration portion penetrating the second scribe lane region; A plurality of first conductive connecting members interposed between the substrate structure and the first double-chip structure and electrically connecting the substrate structure and the first double-chip structure; A plurality of second conductive connecting members interposed between the first double-chip structure and the second double-chip structure and electrically connecting the first double-chip structure and the second double-chip structure; and A semiconductor package comprising a molding member disposed on the substrate structure to cover the first and second double-chip structures and filling the first through-hole and the second through-hole.

Description

Semiconductor Package The present invention relates to a semiconductor package, and more specifically, to a semiconductor package comprising a double-chip structure having a pair of semiconductor chips and a molding member covering the double-chip structure. In the MUF (molded underfill) process, among the stacked chips, the higher a chip is positioned, the faster it can be filled with molding material starting from the outer edges within the same chip. Consequently, the center of the bottommost chip is filled with molding material later, which can result in a void at the bottom of the bottommost chip. Additionally, since the outer edges of the topmost chips are filled with molding material first, warpage may occur during the molding process, which can cause the bumpers of the bottommost chips to be compressed. FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. Figure 2 is a cross-sectional view showing the semiconductor package of Figure 1. Figure 3 is a plan view showing the semiconductor package of Figure 1. FIG. 4 is a cross-sectional view showing the first double-chip structure of FIG. 1. Figure 5 is a plan view showing the first double-chip structure of Figure 4. FIG. 6 is a cross-sectional view showing the second double-chip structure of FIG. 1. FIG. 7 is a plan view showing the second double-chip structure of FIG. 6. FIGS. 8 to 28 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIG. 29 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 30 is a cross-sectional view showing the semiconductor package of FIG. 29. FIG. 31 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 32 is a cross-sectional view showing the semiconductor package of FIG. 31. FIG. 33 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 34 is a cross-sectional view showing the semiconductor package of FIG. 33. FIG. 35 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 36 is a plan view showing the semiconductor package of FIG. 35. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 2 is a cross-sectional view showing the semiconductor package of FIG. 1. FIG. 3 is a plan view showing the semiconductor package of FIG. 1. FIG. 1 is a cross-sectional view cut along the line C1-C1' of FIG. 3. FIG. 2 is a cross-sectional view cut along the line C2-C2' of FIG. 3. FIG. 4 is a cross-sectional view showing the first double-chip structure of FIG. 1. FIG. 5 is a plan view showing the first double-chip structure of FIG. 4. FIG. 4 is a cross-sectional view cut along the line C3-C3' of FIG. 5. FIG. 6 is a cross-sectional view showing the second double-chip structure of FIG. 1. FIG. 7 is a plan view showing the second double-chip structure of FIG. 6. FIG. 6 is a cross-sectional view cut along the line C4-C4' of FIG. 7. Referring to FIGS. 1 to 7, the semiconductor package (10) may include a substrate structure (20), a plurality of double-chip structures (30) sequentially stacked on the substrate structure (20), and a molding member (40) provided on the substrate structure (20) and covering the plurality of double-chip structures (30). In exemplary embodiments, the substrate structure (20) may have a first surface (20a) and a second surface (20b) facing each other. The substrate structure (20) may include a plurality of first substrate pads (23) provided on the first surface (20a) and a plurality of second substrate pads (25) provided on the second surface (20b). Additionally, the substrate structure (20) may further include a plurality of external connection members (27) each disposed on the plurality of second substrate pads (25). For example, the plurality of external connection members may be structures that connect an external device on which the substrate structure is mounted with a semiconductor package. For example, the substrate structure may include a printed circuit board (PCB), an interposer, a buffer chip, etc. For example, if the substrate structure is a buffer chip, the semiconductor package (10) may be a high bandwidth memory (HBM) device comprising a plurality of double-chip structures (30) having a plurality of core chips. However, it will be understood that the present invention is not limited thereto. The substrate structure (20) may have a chip mounting area (MR) in the center. Each of the plurality of first substrate pads (23) may be provided within the chip mounting area (MR) such that at least a portion of them is exposed from the first surface (20a). For example, the chip mounting area may be an area where double-chip structures described later